Network Device Packet Processing Circuit Timestamp Recording

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Solution Overview

Problem

Precision time synchronization protocols, such as PTP, increase packet transmission delay and circuit complexity, particularly in low-latency applications like 5G URLLC services, where packets must be transmitted within strict time limits.

Innovation Solution

A network device architecture with a front-end processing circuit, core circuit, and processor that efficiently processes packets by obtaining and recording timestamps, parsing packets, and modifying them to reduce unnecessary processing, thereby minimizing delay and complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If PTP signal processing is performed on all TX packets and RX packets, then time synchronization precision is improved, but packet transmission delay increases

Engineering Contradiction:
Improvetime synchronization precisionVSAvoidpacket transmission delay
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies local quality by differentiating packet processing based on packet type. PTP packets receive full timestamp processing for synchronization, while data packets skip processing unless they are the first packet of a flow. This selective processing maintains synchronization precision for PTP packets while reducing unnecessary processing delays for data packets.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements preliminary action by establishing flow identification mechanisms and timestamp recording strategies in advance. The system pre-determines which packets require processing based on flow state and packet type, allowing efficient processing decisions to be made without full inspection of every packet.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If PTP signal processing is performed on all packets, then time synchronization is improved, but circuit complexity increases

Engineering Contradiction:
Improvetime synchronization precisionVSAvoidprocessing circuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent reduces circuit complexity by implementing packet-type-specific processing paths. A packet parser identifies packet types and routes them to appropriate processing circuits: PTP packets go to timestamp processing circuits, while data packets follow a simplified path unless flow establishment is needed. This modular approach maintains synchronization functionality while reducing overall circuit complexity.

Inventive Principle:
Principle #3Local quality

3Measurement precision

If timestamp processing is performed on all packets, then time synchronization accuracy is improved, but processing speed decreases

Engineering Contradiction:
Improvetime synchronization accuracyVSAvoidprocessing speed
Core Design Contradiction:
Measurement precisionVSSpeed

Solution Approach 1:

The patent applies local quality by implementing selective timestamp processing. Timestamp processing is performed only on PTP packets and the first data packet of each flow, while subsequent data packets in the same flow skip processing. This maintains high accuracy for synchronization-critical packets while significantly improving overall processing speed.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent applies partial action by processing only the necessary subset of packets for timestamp recording. Instead of processing all packets, the system processes PTP packets and selectively processes data packets based on flow state, achieving sufficient accuracy for synchronization without the excessive processing cost of universal processing.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20240195520A1Network device and network packet processing method
Publication Date: 2024.06.13 REALTEK SEMICON CORP
  • US20240195520A1 patent drawing
  • US20240195520A1 patent drawing
  • US20240195520A1 patent drawing

AI summary

A network packet processing method includes: by a processor of the network device, generating a first predetermined packet, and providing the first predetermined packet to a core circuit of a network device; by a packet parser of the core circuit, parsing the first predetermined packet to obtain a first parsing result corresponding to the first predetermined packet, generating a control information corresponding to the first predetermined packet according to the first parsing result, and providing the first predetermined packet and the control information to a front-end processing circuit; and by the front-end processing circuit, obtaining a first transmitting timestamp corresponding to the first predetermined packet in response to reception of the first predetermined packet, determining to write the first transmitting timestamp into the first predetermined packet or a register according to the control information, and transmitting the first predetermined packet.