Network Device Packet Queueing for Bus Traffic Reduction
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Solution Overview
Problem
Existing computing systems face inefficiencies in delivering packets to network devices, particularly due to high bus traffic and the need for multiple DMA read transactions, which increase latency and resource utilization.
Innovation Solution
Implementing a network device with a header queue and a packet descriptor queue on-board, where the host writes packet headers and DMA descriptors to reduce bus traffic by allowing the network device to fetch payloads directly, thereby minimizing the number of DMA reads from host memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the host writes packet headers and DMA descriptors to on-board queues, then bus traffic is reduced and latency is reduced, but device complexity increases
Solution Approach 1:
The host performs preliminary actions by writing packet headers and DMA descriptors to on-board queues before the network device needs them. This allows the network device to fetch payloads directly without waiting for host memory accesses, reducing latency while the complexity is managed through standardized queue interfaces.
Solution Approach 2:
The packet transmission process is segmented into separate components: packet headers are stored in a header queue, DMA descriptors are stored in a packet descriptor queue, and packet payloads are fetched directly from host memory. This segmentation allows each component to be optimized independently and reduces the need for multiple DMA reads.
2Productivity
If multiple DMA read transactions are used to fetch packet payloads, then packet transmission can proceed, but bus traffic increases and latency increases
Solution Approach 1:
The patent extracts the packet payload fetching operation from the traditional DMA read transaction path. Instead of using multiple DMA read transactions to fetch packet payloads, the network device directly accesses host memory using the DMA descriptors provided in the packet descriptor queue, eliminating unnecessary bus traffic while maintaining packet transmission productivity.
3Productivity
If multiple DMA read transactions are used, then packet payloads can be fetched, but resource utilization increases
Solution Approach 1:
The patent removes the inefficient multiple DMA read transactions from the packet transmission path. By extracting the payload fetching operation and replacing it with direct memory access using pre-provided DMA descriptors, the system maintains packet transmission productivity while significantly reducing resource utilization and energy consumption.
Data Source
AI summary
A packet header is received from a host and written to a header queue. A direct memory access (DMA) descriptor is received from the host and written to a packet descriptor queue. The DMA descriptor points to packet data in a host memory. The packet data is fetched from host memory and the packet header and the packet data are provided to a network interface.