Network Device Programmable Action Processing with Shared Registers
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Solution Overview
Problem
Existing network devices lack efficient methods for flexible and high-performance match-action processing, particularly in handling programmable and stateful actions, which are crucial for packet handling and network management.
Innovation Solution
A network device architecture that shares architectural registers between match-action circuitry and an instruction processor, enabling programmable actions to be executed directly without memory access, with state information management through shared registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If match-action circuitry uses traditional memory access for stateful actions, then state information can be stored and retrieved, but processing execution time increases and performance decreases
Solution Approach 1:
The patent merges the state information storage with the instruction processor's architectural registers. Instead of separate memory access for state information, the state information is stored in and accessed through the same architectural registers that hold instruction operands, eliminating separate memory access cycles and reducing execution time while maintaining stateful action correctness
Solution Approach 2:
The patent performs preliminary action by pre-loading state information into architectural registers before the actual action execution. The match-action circuitry writes state information to architectural registers in advance, so that during action execution, the processor can access state information directly from registers without requiring memory access during the critical execution path
2Adaptability or versatility
If network devices include separate memory and instruction processor for programmable actions, then flexibility is achieved, but die area increases and processing efficiency decreases
Solution Approach 1:
The patent makes the architectural registers universal by enabling them to serve dual purposes: storing instruction operands for the instruction processor and storing state information for match-action operations. This multi-functionality eliminates the need for separate dedicated memory structures, reducing die area while preserving programmable action flexibility through the instruction processor's ability to access and manipulate these shared registers
Solution Approach 2:
The patent combines the instruction processor and match-action circuitry into a unified architecture where both components share the same architectural registers. This merging eliminates redundant memory structures and reduces die area while maintaining the flexibility of programmable actions through the instruction processor's software code execution capability
3Reliability
If match-action circuitry accesses external memory for state information, then stateful actions can be performed, but processing speed decreases due to memory access latency
Solution Approach 1:
The patent performs preliminary action by pre-loading state information into the instruction processor's architectural registers before action execution. The match-action circuitry writes state information to these registers in advance, transforming the slow external memory access into a fast register write operation, while the actual action execution reads from these already-loaded registers, eliminating memory access latency during the critical path
Solution Approach 2:
The patent introduces the architectural registers as an intermediary between external memory and the action execution logic. Instead of direct memory access during action execution, state information is first transferred to the intermediary registers, which then provide fast access during action execution. This intermediary buffer decouples the slow memory access from the fast action execution, improving processing speed while maintaining data accuracy
Data Source
AI summary
A device includes one or more ports, match-action circuitry, and an action processor. The one or more ports are to exchange packets between the device and a network. The match-action circuitry is to match at least some of the packets to one or more rules so as to set respective actions to be performed, at least one of the actions including a programmable action. The instruction processor is to perform the programmable action by running user-programmable software code. The match-action circuitry is to provide the instruction processor information for performing the programmable action.