Network Device Transfer Buffer Dynamic Read Rate Control
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Solution Overview
Problem
Network switching devices face challenges in maintaining stable communications due to underrun conditions, where insufficient data for transmission can lead to incorrect session completion or connection breakdown, and existing technologies struggle to balance guaranteed write and read rates without overutilizing system resources.
Innovation Solution
A method for operating a network device that dynamically adjusts read operations based on transfer buffer occupancy, allowing for a predetermined number of read operations when full and an increased number when occupancy is low, using multiple ports and error-correcting techniques to concurrently perform read and write operations, while distributing data among memory banks to maintain uniform occupancy and free ports for additional reads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the read rate is increased above the guaranteeable read rate, then the device can approach full wire speed, but it is no longer possible to guarantee the certain guaranteeable write rate without increasing system resources
Solution Approach 1:
The system dynamically adjusts the number of read operations per memory cycle based on transfer buffer occupancy. When occupancy is high, a predetermined number of read operations are performed to maintain guaranteed write rate. When occupancy is low, a second number of read operations (greater than predetermined) are performed to approach full wire speed, without requiring additional system resources.
Solution Approach 2:
The system changes the read operation rate parameter based on buffer occupancy conditions. The read rate is adjusted between two states: a conservative rate that guarantees write operations can proceed, and an aggressive rate that maximizes throughput when buffer space is available, thereby resolving the contradiction between reliability and productivity.
2Productivity
If the read rate is increased to approach full wire speed, then data transmission efficiency improves, but system resources must be increased beyond what is needed to guarantee the write rate
Solution Approach 1:
The system performs a second number of read operations (excessive action) only when transfer buffer occupancy is low, allowing the device to approach full wire speed during periods when additional buffer space is available. When occupancy is high, the system performs only the predetermined number of read operations (partial action), maintaining resource usage within guaranteed limits. This selective application of excessive action resolves the contradiction without permanently increasing system resources.
3Productivity
If multiple read and write operations are performed concurrently, then throughput increases, but the complexity of managing memory banks and ports increases
Solution Approach 1:
The transfer buffer is divided into multiple memory banks, each independently manageable. This segmentation allows the system to perform multiple concurrent read and write operations on different banks simultaneously, increasing throughput. The memory controller manages ports for each bank independently, reducing the complexity of coordinating all operations across the entire buffer.
Solution Approach 2:
The memory controller is designed to handle multiple functions: it manages write operations from multiple write ports, read operations from multiple ports, distributes data among memory banks, and monitors occupancy levels. This multi-functionality allows the system to achieve high throughput through concurrent operations without proportionally increasing controller complexity.
Data Source
AI summary
A network device includes a transfer buffer having a plurality of memory banks, and a transfer buffer controller configured to perform a first number of write operations to write processed packets into a memory bank of the transfer buffer, monitor occupancy of the transfer buffer, and when occupancy of the transfer buffer is at least equal to a threshold, perform a predetermined number of read operations during each memory cycle, and when occupancy of the transfer buffer is less than the threshold, perform a second number of read operations, greater than the predetermined number, during each memory cycle. The device concurrently performs multiple read operations and multiple write operations in a single cycle using a plurality of ports. The buffer controller distributes data among the memory banks by allocating write addresses to keep memory occupancy substantially uniform among the memory banks, thereby freeing ports to allow performance of read operations.