Fully Connected Network Edge Compression for Lower Memory Traffic
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Fully connected neural networks face challenges in reducing power consumption and increasing processing speed while maintaining data integrity and reducing data traffic and storage capacity during operations.
Innovation Solution
A control device connected to a learning circuit that compresses edge sequences by merging consecutive invalid bits into one bit and generates a validity determination sequence to differentiate valid and invalid bits, allowing for efficient data input and output through a memory, using an encoding and decoding circuit to manage data flow and reduce unnecessary operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is stored and processed in a fully connected neural network, then the network can perform learning and recognition tasks, but power consumption increases and processing speed decreases
Solution Approach 1:
The patent extracts and removes invalid data (zero values or redundant information) from the edge sequence before storage and processing. By taking out only the necessary valid data for neural network operations, the system reduces memory access requirements and power consumption while maintaining the integrity of essential information needed for learning and recognition tasks.
2Reliability
If all edge data is stored in memory, then data completeness is maintained, but data traffic and storage capacity requirements increase
Solution Approach 1:
The patent applies extraction by identifying and removing invalid edges from the complete edge sequence. The encoding circuit extracts only valid edge information that contributes to neural network functionality, storing merely this essential subset in memory. This maintains data completeness for effective operations while significantly reducing the quantity of stored information and associated storage capacity requirements.
Solution Approach 2:
The patent implements partial action by storing and processing only the necessary portion of edge data rather than the complete dataset. The encoding circuit performs partial encoding to retain only valid edges required for neural network learning, avoiding the excessive storage and processing of redundant invalid data, thus optimizing the balance between data completeness and storage efficiency.
3Ease of operation
If invalid data is processed in the neural network, then data flow is simplified, but processing speed decreases and power consumption increases
Solution Approach 1:
The patent applies preliminary action by performing data encoding and validation before the neural network processing stage. The encoding circuit preliminarily processes the edge sequence to identify and retain only valid data, eliminating invalid entries in advance. This preliminary filtering simplifies the data flow into the neural network and improves processing speed by preventing the network from wasting computational resources on invalid data.
4Device complexity
If consecutive invalid bits are not compressed, then data structure is simpler, but memory access frequency and power consumption increase
Solution Approach 1:
The patent applies merging by combining consecutive invalid bits into a single compressed representation. The encoding circuit merges sequences of invalid bits into condensed forms, reducing the total number of bits that need to be stored and accessed in memory. This compression reduces memory access frequency and associated power consumption while the decoding circuit can efficiently restore the original structure when needed, balancing simplicity and energy efficiency.
Data Source
AI summary
The disclosure relates to an artificial intelligence (AI) system that simulates functions such as cognition and judgment of the human brain by utilizing machine learning algorithms such as deep learning and its applications. In particular, the disclosure provides a method of controlling data input and output of a fully connected network according to an artificial intelligence system and its applications, the method including receiving, from a learning circuit, an edge sequence representing a connection relationship between nodes included in a current layer of the fully connected network, generating a compressed edge sequence that compresses consecutive invalid bits among bit strings constituting the edge sequence into one bit and a validity determination sequence determining valid and invalid bits among the bit strings constituting the compressed edge sequence, writing the compressed edge sequence and the validity determination sequence to the memory, and sequentially reading the compressed edge sequences from the memory based on the validity determination sequence such that the valid bits are sequentially output to the learning circuit.