Network Element External Queue Buffering Design
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Solution Overview
Problem
Ethernet network elements often face network congestion due to limited buffering capacity, leading to packet drops and increased costs when attempting to add larger memories, as it increases die size and requires higher-bandwidth external interfaces.
Innovation Solution
A network element design that combines a small buffered packet switch unit with a large-buffered packet storage unit, where packets arriving on high-traffic interfaces are directed to external queues for buffering, using a flow control mechanism to manage packet transmission and prevent drops, thereby reducing congestion and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large memories are added to increase buffering capacity, then network congestion is reduced, but die size increases and cost increases
Solution Approach 1:
The patent segments the buffering function by introducing external queues in separate memory devices, dividing the buffering capacity from the main ASIC/FPGA die. This allows the network element to achieve large buffering capacity without increasing the die size of the core processing unit, as the external memory resides on separate chips or modules.
Solution Approach 2:
The patent transitions from on-chip buffering to off-chip buffering, moving the storage dimension from the integrated circuit plane to the system board plane. This dimensional shift enables large buffering capacity while keeping the ASIC/FPGA die size small, as external memory devices can be mounted on the circuit board rather than integrated into the chip.
2Reliability
If large memories are added to increase buffering capacity, then network congestion is reduced, but cost increases
Solution Approach 1:
By segmenting the buffering function into external queues, the patent allows use of cost-effective off-chip memory technologies rather than expensive on-chip memory. This segmentation enables the system to achieve large buffering capacity at lower cost by leveraging mature, inexpensive external memory devices instead of costly integrated memory.
3Area of stationary object
If off-chip memory is used to increase buffering capacity, then die size is reduced, but transmission speed decreases
Solution Approach 1:
The patent introduces an intermediary interface layer between the ASIC/FPGA and external memory devices. This interface is optimized for high-speed data transfer, compensating for the slower speed of off-chip memory by providing efficient data pathways and protocols that minimize transmission delays.
Solution Approach 2:
The external queues are pre-configured and pre-synchronized with the packet switch unit, allowing packets to be quickly transferred when needed. This preliminary preparation reduces the effective transmission delay by having the buffering infrastructure ready in advance rather than initializing it on-demand.
Data Source
AI summary
A method and apparatus of a network element that processes a packet in the network element is described. In an exemplary embodiment, the network element receives a data packet that includes a destination address. The network element receives a packet, with a packet switch unit, wherein the packet was received by the network element on an ingress interface. The network element further determines if the packet is to be stored in an external queue. In addition, the network element identifies the external queue for the packet based on one or more characteristics of the packet. The network element additionally forwards the packet to a packet storage unit, wherein the packet storage unit includes storage for the external queue. Furthermore, the network element receives the packet from the packet storage unit and forwards the packet to an egress interface corresponding to the external queue.