Network Structure Etch Mask for Fine Hole Patterns

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Solution Overview

Problem

Conventional photolithography processes face limitations in scaling down pattern sizes for highly integrated semiconductor devices due to resolution constraints, making it difficult to manufacture ICs with small critical dimensions and high density patterns.

Innovation Solution

A method involving the formation of a network structure pattern using alternating line and space burying patterns, followed by etching with a 1-level etch mask to create a pattern of holes with precise dimensions, which allows for the formation of fine patterns beyond the resolution limit of conventional photolithography.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional photolithography processes are used to form patterns, then the manufacturing process is simple and well-established, but the critical dimension cannot be scaled down below the resolution limit

Engineering Contradiction:
Improvecritical dimensionVSAvoidpattern forming process
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The pattern layer is divided into multiple sub-layers including line patterns and space burying patterns. This segmentation allows each sub-layer to be formed with relaxed dimensions that are within photolithography resolution limits, while the combined structure achieves the desired fine critical dimension through self-aligned etching processes

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from forming patterns in a single layer to using multiple stacked pattern layers with alternating line and space burying patterns. This vertical dimensionality enables the creation of fine critical dimensions by combining patterns from multiple layers through self-aligned etching, effectively bypassing the resolution limit of conventional photolithography

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If the pitch and width of features are reduced to increase device integration density, then more devices can be integrated in a narrow area, but the photolithography resolution limit prevents further scaling

Engineering Contradiction:
Improvedevice integration densityVSAvoidfeature size
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The pattern is segmented into line patterns and space burying patterns arranged in alternating sequences. This segmentation allows the formation of features with effective pitch and width smaller than the photolithography resolution limit by combining multiple larger features from different sub-layers through self-aligned etching

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple pattern sub-layers with line patterns and space burying patterns are merged through self-aligned etching processes to create a final pattern with reduced effective pitch and width. The combination of patterns from different layers achieves the desired high integration density with features smaller than the photolithography resolution limit

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If a single-level etch mask is used, then the etching process is simple and fast, but pattern asymmetry occurs leading to deviations in critical dimensions

Engineering Contradiction:
Improveetching process efficiencyVSAvoidcritical dimension uniformity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The etch mask is segmented into multiple pattern sub-layers with alternating line and space burying patterns. This segmentation creates multiple self-aligned etching regions that compensate for each other, preventing pattern asymmetry and ensuring uniform critical dimensions while maintaining a relatively simple single-level etching process

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The alternating arrangement of line patterns and space burying patterns creates a symmetric overall structure that compensates for local asymmetries during etching. This deliberate asymmetric design at the sub-layer level results in symmetric etching behavior at the final pattern level, minimizing critical dimension deviations

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS9960039B2Method of forming pattern and method of manufacturing integrated circuit device by using the same
Publication Date: 2018.05.01 SAMSUNG ELECTRONICS CO LTD
  • US9960039B2 patent drawing
  • US9960039B2 patent drawing
  • US9960039B2 patent drawing

AI summary

A method of forming a pattern includes forming a first level pattern layer on a feature layer on a substrate. The first level pattern layer includes a plurality of first line patterns and a plurality of first space burying patterns. The first line patterns extend parallel to one another in a first direction and the first space burying patterns extend parallel to one another in the first direction with first line patterns alternately disposed with first space burying patterns A portion of the plurality of first space burying patterns may be removed to form a second direction pattern space extending intermittently or continuously in the first level pattern layer. A second burying layer filling the second direction pattern space may be formed to form a network structure pattern. The feature layer may be etched with the network structure pattern as an etch mask to form a pattern of holes.