Network File Server Thread Scheduling and Interrupt Affinity

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Solution Overview

Problem

Network file servers with multiple core central processing units face challenges in efficiently distributing the execution of real-time and general-purpose code threads among CPUs, leading to performance issues due to interference between conflicting tasks and imbalanced CPU usage.

Innovation Solution

A network file server architecture that assigns interrupts and code threads to core CPUs in a way that hard affinity threads are executed exclusively by specific CPUs, while soft affinity threads are distributed across CPUs for load balancing, with network adapter interrupts mapped to a single CPU and disk adapter interrupts distributed across multiple CPUs to avoid interference, ensuring that disk adapter interrupts do not interrupt network stack processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple core CPUs are used to process interrupts and code threads, then processing capacity and throughput are improved, but interference between conflicting tasks increases and CPU usage becomes imbalanced

Engineering Contradiction:
Improveprocessing capacityVSAvoidtask interference
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments interrupt handling and code thread execution into distinct CPU assignments. Specifically, it divides CPUs into groups: some CPUs are dedicated to handling disk adapter interrupts, while other CPUs handle network adapter interrupts and execute network stack code threads. This segmentation prevents interference between disk I/O operations and network processing, allowing each CPU group to operate independently without task conflicts.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by assigning different operational characteristics to different CPUs. Each CPU is given a specific role (disk interrupt handling, network interrupt handling, or code thread execution) based on its capabilities and the requirements of the tasks it handles. This localized specialization ensures that each CPU operates optimally for its assigned functions, improving overall system reliability while maintaining high productivity.

Inventive Principle:
Principle #3Local quality

2Productivity

If interrupts are distributed across multiple CPUs, then interrupt handling capacity is improved, but latency in responding to client requests increases

Engineering Contradiction:
Improveinterrupt handling capacityVSAvoidresponse latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements preliminary action by pre-assigning specific CPUs to handle specific types of interrupts and code threads. During system initialization, the interrupt controller is configured to route disk adapter interrupts to designated CPUs, and the scheduler is set up to allocate network stack code threads to specific CPUs. This preliminary assignment eliminates the need for dynamic decision-making during interrupt handling, reducing latency while maintaining high interrupt handling capacity across multiple CPUs.

Inventive Principle:
Principle #10Preliminary action

3Ease of operation

If code threads are dynamically assigned to CPUs, then load balancing is improved, but CPU usage imbalance and task interference occur

Engineering Contradiction:
Improveload balancingVSAvoidCPU usage efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent implements a dynamic code thread assignment mechanism that operates within the constraints of static interrupt assignments. The scheduler dynamically allocates network stack code threads to CPUs based on current system state, but only to CPUs that are not currently handling disk adapter interrupts. This dynamic allocation achieves load balancing for code threads while preventing the CPU usage imbalance and task interference that would result from dynamic reassignment of interrupt handling duties.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8180973B1Servicing interrupts and scheduling code thread execution in a multi-CPU network file server
Publication Date: 2012.05.15 EMC IP HLDG CO LLC
  • US8180973B1 patent drawing
  • US8180973B1 patent drawing
  • US8180973B1 patent drawing

AI summary

Interrupts and code threads are assigned in a particular way to the core CPUs of a network file server in order to reduce latency for processing client requests for file access. Threads of the network stack are incorporated into real time threads that are scheduled by a real-time scheduler and executed exclusively by a plurality of the core CPUs that are not interrupted by disk adapter interrupts so that the disk adapter interrupts do not interrupt execution of the network stack. Instances of a storage access driver are hard affinity threads, and soft affinity threads include a multitude of instances of a thread of the file system stack for file access request processing so that file access request processing for a multitude of concurrent file access requests is load balanced over the core CPUs.