Network FPGA Programming Using Payload-Only Frame Writing
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Solution Overview
Problem
Existing methods for programming Field Programmable Gate Arrays (FPGAs) via networks face performance limitations, complexity, cost issues, and manageability challenges, particularly due to slow indirect updates via JTAG and speed limitations with direct updates from non-volatile memory, as well as increased complexity and costs with auxiliary processors.
Innovation Solution
A method utilizing a predetermined communications protocol to establish a connection between the FPGA and an external master, employing a permanently programmed glue logic component with a digital counter and comparator to parse and write payload sections directly, enabling the FPGA to boot from the network with minimal external devices and reducing board space and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If indirect update via JTAG is used, then the non-volatile memory can be updated, but the process is too slow and requires a complex external device
Solution Approach 1:
The patent extracts the update capability from the slow JTAG interface and implements a separate, dedicated parallel interface between the external master and non-volatile memory. This dedicated interface operates independently from the JTAG chain, allowing simultaneous FPGA operation and memory updates at much higher speeds.
Solution Approach 2:
The patent introduces an external master device as an intermediary that mediates between the network and the non-volatile memory. This external master handles the complex update operations, parsing the incoming bitstream and writing it to the memory, thereby freeing the FPGA to operate normally while updates occur in parallel.
2Productivity
If direct update via FPGA is used, then the update is faster and less disruptive, but the speed is limited due to the directly attached non-volatile memory
Solution Approach 1:
The patent introduces an external master device as an intermediary that mediates between the network and the non-volatile memory. This external master handles the complex update operations, parsing the incoming bitstream and writing it to the memory, thereby freeing the FPGA to operate normally while updates occur in parallel.
3Adaptability or versatility
If auxiliary processor is added for network boot, then the FPGA can boot from network, but the board space and complexity increase
Solution Approach 1:
The external master device is designed with multi-functionality, serving both as a network interface controller and as a processor for handling FPGA configuration updates. This single device performs multiple roles that would otherwise require separate components, reducing overall system complexity.
Solution Approach 2:
The patent merges the network interface functionality with the configuration management functionality into a single external master device. This consolidation eliminates the need for separate auxiliary processors and reduces the number of external components required on the FPGA board.
Data Source
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AI summary
The invention relates to a method for programming a Field Programmable Gate Array (FPGA) via a network, the network being operated according to a predetermined communications protocol, wherein the method comprises the steps of - establishing, via the network, a communications connection between the FPGA to an external master in the network; - setting the FPG A into a programming mode; - receiving an FPGA programming image for programming the FPGA, the FPGA programming image being transmitted from the external master to the FPGA according to the predetermined network communications protocol in a sequence of frames, each frame comprising a payload section and protocol overhead section, each payload section comprising a portion of the programming image, - parsing the sequence of frames, and - enabling FPGA writing only during receiving the payload section of each of the frames received and writing the portion of the programming data of the payload section into the FPGA, wherein the steps of receiving the FPGA programming image and parsing the sequence of frames is performed by a permanently programmed or hardwired logic component. Further, the present invention relates to a network configuration for carrying out the method.