Network Interface Buffer Segmentation for Memory Bottleneck Resolution
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Solution Overview
Problem
Current network interfaces in storage systems face performance degradation due to memory bottlenecks, particularly when handling protocols like iSCSI and NVMe TCP, which require multiple memory accesses and are limited by hardware constraints such as board area and power limitations, making it difficult to support multiple protocols efficiently.
Innovation Solution
A network interface configuration that includes a general-purpose processor, memory, and cache, which secures multiple buffers of varying sizes, manages buffer allocation, and optimizes cache usage to reduce memory access frequency and prevent cache overflow, allowing for flexible protocol support and efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory chips are mounted to increase buffer capacity, then memory performance is improved, but board area and power consumption increase
Solution Approach 1:
The patent segments the buffer into multiple buffers of different sizes (first buffer, second buffer, third buffer) with different retention policies. This allows the system to achieve required buffer capacity through strategic allocation rather than uniformly increasing all buffer sizes, thereby reducing total memory requirements and board area.
Solution Approach 2:
Different buffers are assigned different retention periods based on local characteristics of data access patterns. The first buffer has a shorter retention period for frequently accessed data, while the second and third buffers have longer retention periods for less frequently accessed data. This localized differentiation optimizes memory usage without requiring uniform expansion of all buffers.
2Quantity of substance
If multiple memory chips are mounted to increase buffer capacity, then memory performance is improved, but power consumption increases
Solution Approach 1:
The buffer is segmented into multiple buffers with different retention periods, allowing the system to achieve required buffer capacity through selective allocation rather than uniformly expanding all buffers. This reduces total active memory and consequently power consumption.
Solution Approach 2:
Different retention periods are applied locally to different buffers based on data access patterns. By extending retention periods for less frequently accessed data in specific buffers, the system reduces the need for continuous memory access and refresh operations, thereby lowering power consumption while maintaining adequate buffer capacity.
3Adaptability or versatility
If CPU is used for protocol processing, then protocol support flexibility is improved, but processing speed decreases due to CPU resource consumption
Solution Approach 1:
The patent introduces a buffer as an intermediary between the network interface and the CPU. By pre-storing protocol data in the buffer with appropriate retention periods, the system reduces the frequency and complexity of CPU interventions, allowing flexible protocol support while maintaining high processing speed through minimized CPU resource consumption.
4Productivity
If buffer size is increased to reduce memory access frequency, then performance is improved, but cache overflow risk increases
Solution Approach 1:
The buffer is divided into multiple buffers with different retention periods. This segmentation allows the system to achieve performance improvements through reduced memory access frequency in specific buffers while controlling cache overflow risk by limiting the retention period in other buffers, thereby balancing performance and reliability.
Solution Approach 2:
Different retention periods are applied locally to different buffers based on data access patterns and cache overflow risk assessment. By extending retention periods only for buffers with low overflow risk and shorter periods for high-risk buffers, the system optimizes performance while maintaining reliability through localized control.
Data Source
AI summary
A network interface includes a processor, memory, and a cache between the processor and the memory. The processor secures a plurality of buffers for storing transfer data in the memory, and manages an allocation order of available buffers of the plurality of buffers. The processor returns a buffer released after data transfer to a position before a predetermined position of the allocation order.