Network Interface Bus Jitter Reduction via Timeslot Scheduling

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

In real-time controllers, the integration of non-deterministic Ethernet and deterministic buses leads to increased bus jitter due to unpredictable data arrival times from the Ethernet bus, which can postpone or prevent memory access for deterministic data.

Innovation Solution

A Network Interface (NI) is coupled to memory, receiving a schedule that reserves timeslots for deterministic data transfer and buffers non-deterministic data until available timeslots, ensuring deterministic data is transferred only during reserved timeslots, thus avoiding collisions and maintaining deterministic data integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If non-deterministic Ethernet data is allowed to access the shared bus freely, then network communication flexibility is improved, but bus jitter increases and deterministic data transfers are disrupted

Engineering Contradiction:

Improvenetwork communication flexibilityVSAvoidbus jitter

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The bus access time is segmented into reserved timeslots and available timeslots. Reserved timeslots are allocated exclusively for deterministic data transfers, while available timeslots are allocated for non-deterministic Ethernet data transfers. This segmentation isolates deterministic traffic from the variability of Ethernet traffic, reducing bus jitter while maintaining network flexibility.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The bus operates in periodic cycles with alternating reserved and available timeslots. This periodic structure ensures that deterministic data transfers occur at predictable intervals with bounded latency, while Ethernet data can be transmitted during available timeslots without causing jitter to deterministic communications.

Inventive Principle:

Principle #19Periodic action

2Ease of operation

If Ethernet data arrives at any time on the shared bus, then network communication autonomy is improved, but memory access for deterministic data is postponed or prevented

Engineering Contradiction:

Improvenetwork communication autonomyVSAvoidmemory access delay

Core Design Contradiction:

Ease of operationVSLoss of time

Solution Approach 1:

Reserved timeslots are pre-allocated for deterministic data transfers before Ethernet data arrives. The controller prepares to receive deterministic data at these predetermined times, ensuring that memory access for deterministic data is not postponed or prevented by random Ethernet traffic arrivals.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The shared bus acts as an intermediary resource that is managed through timeslot allocation. By mediating access to the bus through reserved and available timeslots, the system ensures that deterministic data transfers occur without interference from Ethernet data, preventing memory access delays while maintaining network autonomy.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Adaptability or versatility

If both deterministic and non-deterministic buses share the peripheral IO bus, then device integration is improved, but data transfer reliability deteriorates due to collision

Engineering Contradiction:

Improvedevice integrationVSAvoiddata transfer reliability

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The shared peripheral IO bus is segmented into reserved timeslots for deterministic devices and available timeslots for Ethernet devices. This segmentation allows both deterministic and non-deterministic buses to share the same physical medium while preventing collisions, as each device type has dedicated time windows for data transfer.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS8295287B2Network traffic shaping for reducing bus jitter on a real time controller

Publication Date: 2012.10.23 NATIONAL INSTRUMENTS CORP

AI summary

System and method for controlling access to a bus. A Network Interface (NI) is coupled to a memory via the bus, and receives a schedule to a Direct Memory Access (DMA) controller on the NI. The schedule indicates one or more timeslots reserved for transmission of deterministic data, and further indicates one or more available timeslots which are not reserved for transmission of deterministic data. The NI receives first data for transmission onto the bus, during a first timeslot of the available timeslots, where the first data are received in a non-deterministic manner, and determines that the first timeslot is a reserved timeslots based on the schedule. The first data are buffered in a buffer memory during the first timeslot, and transferred to the first memory via the bus during a second timeslot after the buffering, where the second timeslot is one of the one or more available timeslots.