Network Interface Cell Engine Aggregating Processor Circuits
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Solution Overview
Problem
Current network interfaces face challenges in enhancing the capacity of network nodes due to the mismatch between high-bandwidth optical components and limited capacity of available packet processors, leading to inefficient bandwidth utilization and lower effective bandwidth in packet-switched networks.
Innovation Solution
The system employs a network interface with a cell engine that fragments packets into header and body cells, assigns sequence numbers, and distributes them across multiple processor circuits and transmission paths using load-balancing methods, allowing for reassembly into packets at the receiving end, thereby aggregating smaller bandwidth processor circuits to create virtual higher-capacity interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple parallel links are used to increase bandwidth capacity, then the aggregate bandwidth is improved, but the effective bandwidth is reduced due to load distribution inefficiency
Solution Approach 1:
The patent segments packets into fixed-size cells (e.g., 64-byte SDH/SONET cells) that can be independently distributed across multiple parallel processor circuits. This segmentation allows each cell to be handled by any available processor circuit without requiring complex load distribution algorithms, thereby achieving both high bandwidth capacity and high effective bandwidth utilization.
Solution Approach 2:
The patent introduces a cell engine as an intermediary component that sits between the optical interface and multiple processor circuits. The cell engine performs cell extraction, reassembly, and distribution functions, enabling efficient load balancing across processor circuits while maintaining full utilization of available bandwidth capacity.
2Quantity of substance
If Link Aggregation Group (LAG) with Equal Cost Multi-Path (ECMP) routing is used, then bandwidth aggregation is achieved, but load distribution efficiency drops below 100%
Solution Approach 1:
By segmenting data into fixed-size cells rather than using variable-length packets, the system eliminates the need for complex ECMP hashing algorithms. Each cell can be uniformly distributed across parallel links, achieving 100% bandwidth efficiency without the losses inherent in packet-based load distribution.
Solution Approach 2:
The patent changes the fundamental parameter of data unit size from variable-length packets to fixed-size cells. This parameter change enables more efficient memory allocation, processing, and load distribution across multiple processor circuits, eliminating the bandwidth efficiency losses associated with traditional LAG/ECMP implementations.
3Speed
If high-bandwidth optical components are used, then transmission capacity is improved, but processor circuit capacity becomes the limiting factor
Solution Approach 1:
The patent segments high-speed optical data streams into smaller fixed-size cells that can be processed by multiple lower-capacity processor circuits in parallel. This segmentation allows the system to aggregate the processing capacity of multiple circuits to match the high transmission capacity of optical components, eliminating the processor bottleneck.
Solution Approach 2:
The patent transitions from single-thread packet processing to multi-dimensional cell processing by distributing cells across multiple processor circuits simultaneously. This dimensional change in processing architecture enables the system to scale processing capacity linearly with the number of processor circuits, matching the scalability of optical transmission capacity.
Data Source
AI summary
A system having a first and second interfaces is described. At least one of the first and second interfaces has a cell engine, a first processor circuit, a second processor circuit, and a first and second transponder. The first processor circuit is coupled with the first transponder and the cell engine so as to transmit a header cell to the cell engine. The second processor circuit is coupled with the second transponder and the cell engine so as to transmit a body cell to the cell engine. The system may aggregate the processing capacity of several processor circuits to form larger capacity logical interfaces. Packets may be fragmented into a header cell including the packet header and body cells including the packet payload and then transmit and reassemble the packet. The header cells may be fully handled by the processor circuit, while body cells may be passed on without processing.