Multiple Network Interface Cores for Scalable Message Throughput
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Solution Overview
Problem
Network interface controllers (NICs) face challenges in maintaining message throughput as network bandwidth increases, with the growth of multi-core processors limiting message size and clock rates, and existing solutions like multi-rail systems face scalability issues due to resource contention and inefficiencies.
Innovation Solution
Implementing multiple network interface cores within a single integrated circuit, allowing for resource sharing and replication to enhance message rate without the challenges of multi-rail systems, and supporting both Message Passing Interface (MPI) and Partitioned Global Address Space (PGAS) programming models with discrete hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple network interface cores are implemented within a single integrated circuit, then message rate throughput increases and silicon area efficiency improves, but device complexity increases
Solution Approach 1:
The network interface controller is divided into multiple independent network interface cores (e.g., NIC core 104, NIC core 108) that can process messages in parallel. Each core has its own processing units and can operate independently to handle different message streams, thereby increasing throughput while maintaining manageable complexity through modular architecture
Solution Approach 2:
Multiple network interface cores are merged into a single integrated circuit device, allowing them to share common resources such as address translation units, error correction logic, and interconnect structures. This consolidation achieves high throughput while improving silicon area efficiency compared to using separate NIC devices
2Area of stationary object
If multiple network interface cores share common resources, then silicon area efficiency improves, but resource contention may occur
Solution Approach 1:
Common resources such as the address translation unit and error correction logic serve multiple network interface cores simultaneously, enabling resource sharing and improving silicon area efficiency. These universal components are designed to handle requests from any core, providing multi-functional capability that reduces overall device footprint
Solution Approach 2:
A resource arbitration mechanism or mediator structure is implemented to manage access to shared resources among multiple network interface cores. This intermediary layer coordinates resource allocation to minimize contention and ensure reliable operation, allowing efficient resource sharing without sacrificing performance
3Productivity
If network interface controllers increase parallelism to match bandwidth growth, then message rate improves, but device complexity increases
Solution Approach 1:
The controller is segmented into multiple parallel network interface cores that independently process messages, enabling the system to achieve high message rates by exploiting parallelism. Each core operates with its own processing logic, allowing the system to scale throughput without requiring a single monolithic complex controller
Solution Approach 2:
Instead of increasing the complexity of a single sequential processing path, the solution adds a dimensional aspect by introducing multiple parallel cores. This transforms the problem from sequential processing complexity to parallel architecture complexity, achieving higher throughput through dimensional expansion rather than vertical complexity increase
Data Source
AI summary
A network interface controller and network interface control method comprising providing a single integrated circuit as a network interface controller and employing a plurality of network interface cores on the single integrated circuit.