Programmable Network Interface Offloading Computer Vision Media Processing

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Solution Overview

Problem

In highly virtualized environments, significant server resources are expended processing tasks such as hypervisors, container engines, network and storage functions, security, and network traffic, which can be offloaded to programmable network interface devices like infrastructure processing units (IPUs) and data processing units (DPUs).

Innovation Solution

The implementation of programmable network interface devices with accelerators and network connectivity allows for the offloading of media processing tasks from server CPUs to these devices, specifically through the management of computer vision (CV) pipelines. This involves a decomposed CV pipeline where media processing is performed in the programmable network interface device, reducing latency and improving resource utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If media processing tasks are performed on server CPUs in highly virtualized environments, then general-purpose computing flexibility is maintained, but server resources are significantly expended and processing latency increases

Engineering Contradiction:
Improveprocessing throughputVSAvoidprocessing latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent segments the computer vision pipeline into distinct functional modules (media processing, preprocessing, feature extraction, object detection, etc.) that can be distributed across different processing units. Media processing tasks are separated from general-purpose CPU operations and assigned to specialized hardware accelerators, enabling parallel execution and reducing overall processing latency while maintaining system productivity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a media processing accelerator as an intermediary component between the network interface device and the server CPU. This intermediary handles the computationally intensive media processing tasks (decoding, format conversion, resolution adjustment) that would otherwise consume significant CPU resources, thereby reducing both processing latency and CPU resource expenditure while maintaining system flexibility.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If server resources are used for infrastructure processing tasks, then comprehensive control and management are achieved, but resource availability for user applications decreases

Engineering Contradiction:
Improveinfrastructure management capabilityVSAvoiduser application performance
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent extracts infrastructure processing tasks (media processing, network packet processing, storage operations) from the server CPU and relocates them to specialized hardware components (media processing accelerators, network interface devices with integrated processors). This extraction maintains comprehensive infrastructure management capability while freeing up significant CPU resources for user applications, thereby resolving the resource contention issue.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent implements universal media processing accelerators that can handle multiple types of infrastructure tasks (video decoding, encoding, format conversion, resolution adjustment) through programmable architectures. These multi-functional accelerators provide comprehensive infrastructure management capability while consuming fewer overall server resources compared to using general-purpose CPUs for all infrastructure tasks.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Speed

If dedicated media processing hardware is introduced, then processing speed and resource efficiency improve, but device complexity increases

Engineering Contradiction:
Improvemedia processing speedVSAvoidsystem architecture complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent implements a nested architecture where media processing accelerators are integrated within network interface devices, which themselves are connected to the server system. This nested structure (accelerators nested in NICs nested in server system) consolidates multiple functions into hierarchical layers, improving media processing speed while managing device complexity through organized integration rather than scattered components.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent merges media processing functionality with network interface device capabilities, creating integrated components that handle both network communication and media processing. This merging reduces the number of separate devices and interfaces required, thereby improving processing speed while actually reducing overall system complexity through consolidation rather than addition of components.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20250068457A1Computer vision pipeline management in programmable network interface device
Publication Date: 2025.02.27 INTEL CORP
  • US20250068457A1 patent drawing
  • US20250068457A1 patent drawing
  • US20250068457A1 patent drawing

AI summary

An apparatus includes a host interface; a network interface; and a programmable circuitry communicably coupled to the host interface and the network interface, the programmable circuitry comprising one or more processors to implement network interface functionality and to: determine portions of a set of computer vision (CV) processes to be deployed on the programmable circuitry and a host device, wherein the host device to be communicably coupled to the programmable network interface device; access instructions to cause the portions of the set of the CV processes to be deployed on the host device and the programmable network interface device; and wherein a media processing portion of the set of the CV processes is to be deployed to the programmable circuitry, and wherein the programmable circuitry is to utilize media processing hardware circuitry hosted by the apparatus to perform the media processing portion.