Network Interface Circuit Interrupt-Driven Memory Update

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Solution Overview

Problem

The existing network interface circuits experience inefficiencies in data transmission due to a period of waiting between the end of one packet transmission and the start of the next, which reduces overall network transmission efficiency.

Innovation Solution

The network interface circuit sends an interrupt request signal as soon as packet data is processed by the medium control module, allowing the memory access circuit to store the next packet data in memory while the medium control module transmits the previous packet, thereby shortening the interval between packet transmissions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the memory access circuit waits for the medium control module to finish transmitting a packet before storing the next packet data, then data transmission accuracy is maintained, but network transmission efficiency deteriorates due to idle waiting periods

Engineering Contradiction:
Improvenetwork transmission efficiencyVSAvoididle period between packet transmissions
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The memory access circuit performs preliminary action by storing the next packet data in the memory buffer before the current packet transmission is completely finished. The interrupt request signal mechanism allows the memory to be updated in advance, eliminating the idle waiting period between packet transmissions while maintaining data accuracy through the interrupt-driven architecture.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the memory updating rate is increased to reduce idle time, then network transmission efficiency improves, but data accuracy may deteriorate due to potential data overwriting

Engineering Contradiction:
Improvedata updating rateVSAvoiddata transmission accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The interrupt request signal serves as a feedback mechanism that coordinates between the medium control module and memory access circuit. When the medium control module finishes processing a packet, it generates an interrupt request signal that triggers the memory access circuit to update the memory buffer, ensuring that data is only overwritten when the previous data has been fully processed, thus maintaining accuracy while enabling continuous updates.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS7451240B2Method and related circuit for increasing network transmission efficiency by increasing a data updating rate of a memory
Publication Date: 2008.11.11 VIA TECH INC
  • US7451240B2 patent drawing
  • US7451240B2 patent drawing
  • US7451240B2 patent drawing

AI summary

A network interface circuit or card has a memory and a medium control module for transmitting data stored in the memory to a network. The method includes: when a packet data is transmitted (such as completely transmitted) from the memory to the medium control module, making the memory send an interrupt request such that a new packet data can be read into the memory. This results in increased data transmission efficiency in the network interface circuit.