Network Interface Packet Classifier for Throughput and Latency
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Solution Overview
Problem
Existing networked computer systems face limitations in achieving high functional efficiencies while maintaining generality and modularity, particularly in terms of network throughput, latency, packet rate, session rate, and processing overhead, due to constraints such as limited queues between network interfaces and processors, asynchronous interrupt notifications, and DMA latency.
Innovation Solution
A network interface unit is designed with an unconstrained number of queues, coordinating shared queue servicing, providing affinity between stateful sessions and processors, and minimizing asynchronous notification overheads, while integrating multiple processor cores and processing threads to enhance packet processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple queues are provided between network interface and processors, then network throughput is improved, but device complexity increases
Solution Approach 1:
The network interface is divided into multiple independent queues, each capable of servicing packets independently. This segmentation allows parallel processing across multiple processor cores, improving throughput while maintaining manageable complexity through modular queue structures.
Solution Approach 2:
The patent introduces a multi-dimensional queue architecture where queues are organized not only by network interface but also by processor core affinity. This additional dimension enables scalable throughput by allowing queues to be distributed across multiple processing dimensions without linearly increasing coordination complexity.
2Ease of operation
If asynchronous interrupt notifications are used, then packet arrival notification is enabled, but processing overhead increases
Solution Approach 1:
The patent introduces an intermediary mechanism that buffers and batches interrupt notifications before delivering them to processors. This intermediary layer reduces the frequency and overhead of actual interrupt processing while maintaining responsive packet arrival notification, effectively decoupling the notification function from the processing overhead.
3Productivity
If DMA is used for network data access, then data movement capability is improved, but latency increases
Solution Approach 1:
The system performs preliminary actions by pre-positioning data in memory buffers and pre-configuring DMA transfer parameters before actual network data arrival. This preparation reduces the critical path latency of DMA operations while maintaining high data movement capability, as the heavy lifting of data preparation is done in advance rather than during time-critical transfer windows.
4Productivity
If processing resources are increased, then system performance is improved, but scalability is constrained by coordination requirements
Solution Approach 1:
The patent assigns specific queues to specific processor cores based on affinity relationships, creating local quality optimizations. Each processor core becomes specialized in servicing particular queues, reducing cross-core coordination overhead. This local specialization allows performance to scale with resource additions while minimizing the coordination complexity that would otherwise grow linearly with resource scale.
Data Source
AI summary
A network system which includes a plurality of processing entities, an interconnect device coupled to the plurality of processing entities, a memory system coupled to the interconnect device and the plurality of processing entities, a network interface unit coupled to the plurality of processing entities and the memory system via the interconnect device. The network interface includes a memory access module and a packet classifier. The memory access module includes a plurality of parallel memory access channels. The packet classifier provides a flexible association between packets and the plurality of processing entities via the plurality of memory access channels.