Network Interface Queue Segmentation for Throughput
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Solution Overview
Problem
Existing networked computer systems face limitations in achieving high functional efficiencies while maintaining generality and modularity, particularly in terms of network throughput, latency, packet rate, session rate, and processing overhead, due to constraints such as limited queues between network interfaces and processors, asynchronous interrupt notifications, and multiple packet memory representations.
Innovation Solution
A network interface unit is designed with an unconstrained number of queues, coordinating shared queue servicing, providing affinity between stateful sessions and processors, and minimizing asynchronous notification overheads, while allowing multiple packet memory representations and parallel memory access channels to enhance DMA bandwidth and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processors service a network interface with shared queues, then processing throughput is improved, but coordination overhead increases and packet ordering becomes difficult to preserve
Solution Approach 1:
The patent segments the queue servicing function by dedicating one processor to each queue. This eliminates the need for coordination between processors since each processor independently manages its assigned queue, preserving packet ordering within each queue while achieving high throughput through parallel processing of multiple queues.
2Speed
If asynchronous interrupt notifications are used for packet arrival, then processor responsiveness is improved, but processing penalties increase disproportionately
Solution Approach 1:
The patent implements preliminary action by having processors periodically poll for packet arrivals instead of waiting for asynchronous interrupts. This allows processors to proactively check for work in their assigned queues, eliminating the disproportionate processing penalties associated with interrupt handling while maintaining responsiveness to packet arrivals.
3Use of energy by moving object
If DMA semantics are used for network data access, then memory access efficiency is improved, but latency increases and bandwidth decreases compared to processor memory accesses
Solution Approach 1:
The patent merges the network interface's memory access operations with the processor's memory access operations by having the dedicated processor service the queue directly through normal memory access mechanisms. This eliminates the separate DMA path and its associated latency and bandwidth limitations, allowing network data to be accessed with the same efficiency as processor memory accesses.
4Reliability
If packet ordering is preserved across multiple queues, then network protocol compliance is improved, but queue coordination complexity increases
Solution Approach 1:
The patent applies segmentation by assigning one processor to each queue, which naturally preserves packet ordering within each queue since the dedicated processor services packets in sequential order. Multiple queues can then be used in parallel without coordination complexity, as each queue-operating-point combination is independently managed by its own processor.
Data Source
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AI summary
A network system which includes a plurality of processing entities, an interconnect device coupled to the plurality of processing entities, a memory system coupled to the interconnect device and the plurality of processing entities, a network interface unit coupled to the plurality of processing entities and the memory system via the interconnect device. The network interface includes a memory access module and a packet classifier. The memory access module includes a plurality of parallel memory access channels. The packet classifier provides a flexible association between packets and the plurality of processing entities via the plurality of memory access channels.