Network Interface Multi-Stream Scheduling for Low-Jitter TSN
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Solution Overview
Problem
Current network interface cards (NICs) are unable to efficiently schedule multiple data streams belonging to the same traffic class, leading to software-induced latency and jitter, which is undesirable for hard real-time applications.
Innovation Solution
Implementing a mechanism in NICs to directly schedule multiple streams per traffic class using modified descriptors with parameters like launch time offset, gating cycle number, and reduction ratio, along with a dedicated DMA channel and prefetch cache, to achieve precise packet scheduling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software scheduling is used to manage multiple data streams, then flexibility and control are improved, but latency and jitter increase due to software processing overhead
Solution Approach 1:
The patent replaces software-based scheduling with hardware-based scheduling in the network interface card. The hardware scheduler circuit directly manages multiple data streams using descriptor rings and timing parameters, eliminating the need for software intervention in packet scheduling operations. This substitution of mechanical/software system with hardware system resolves the contradiction by providing both flexibility (through configurable descriptors) and low latency (through direct hardware execution).
Solution Approach 2:
The patent introduces descriptor rings as an intermediary data structure that bridges the application layer and hardware scheduler. Descriptors contain pre-configured scheduling parameters (timing, priority, stream identification) that enable the hardware scheduler to autonomously manage multiple streams without software involvement. This intermediary mechanism allows flexible scheduling control while maintaining deterministic timing behavior.
2Quantity of substance
If multiple data streams are scheduled per traffic class, then stream capacity is improved, but device complexity increases
Solution Approach 1:
The patent segments the scheduling mechanism into distinct descriptor structures, each representing a single data stream. Multiple descriptors can be linked together in descriptor rings, allowing the hardware scheduler to manage multiple streams through simple, repetitive processing of individual descriptor units. This segmentation enables scalable stream capacity without proportionally increasing overall system complexity.
Solution Approach 2:
The patent implements descriptor rings that can accommodate more streams than currently needed, allowing the system to start with fewer streams and dynamically add more as required. The descriptor ring structure pre-allocates space for multiple stream descriptors, enabling incremental activation of streaming capacity without requiring complete system redesign. This partial action approach manages complexity by activating only necessary streams while maintaining capability for expansion.
3Speed
If hardware scheduling is implemented, then processing speed is improved, but power consumption increases
Solution Approach 1:
The patent implements a gating mechanism that periodically enables and disables scheduling operations based on traffic requirements. The hardware scheduler operates in discrete gating cycles, activating packet scheduling only when data is present in the buffer. During idle periods, the scheduler remains inactive, consuming minimal power. This periodic action maintains high processing speed when needed while significantly reducing average power consumption during low-traffic conditions.
Solution Approach 2:
The hardware scheduler is designed to autonomously manage packet scheduling without requiring continuous software supervision or intervention. Once configured with descriptor rings, the scheduler independently processes packets according to embedded timing parameters and stream priorities. This self-service capability eliminates the need for continuous software-hardware interaction, reducing overall system power consumption while maintaining high-speed hardware-based scheduling.
Data Source
AI summary
A network interface device for implementing multi-stream scheduling for time sensitive networking includes direct memory access (DMA) circuitry, comprising: descriptor parsing circuitry to read a packet descriptor from a descriptor cache, wherein the packet descriptor includes at least one scheduling control parameter including: a launch time offset, a gate cycle offset, or a reduction ratio; wherein the packet descriptor is associated with a packet stream having a traffic class; and scheduling circuitry to schedule packets from the packet stream for transmission using the at least one scheduling control parameter.