Network Interface Tag Matching for Ordered Message Storage
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Solution Overview
Problem
Existing message passing protocols in parallel computing, such as MPI, face inefficiencies when handling variable-length messages due to unknown message arrival order, leading to CPU cycle and memory bandwidth overhead, and require improved delivery to specific application address ranges.
Innovation Solution
Implementing a tag-matching send/receive model (TMSR) that offloads tag matching operations to network interface devices, using Matched Queue Pairs (MQPs) with completion queues (CQs), Matched Send Queues (MSQs), and Matched Receive Queues (MRQs) to ensure efficient delivery and ordering of messages, supported by a 128-bit tag value and mask for precise matching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If messages are delivered in arrival order to receive buffers, then message delivery is simple, but CPU cycles and memory bandwidth overhead increase significantly
Solution Approach 1:
The patent introduces an intermediary mechanism (tag matching system with unexpected message buffers) between the network interface and application memory. When a message arrives, the system first checks if there's a matching receive operation using tag comparison. If no match is found, the message is stored in an unexpected message buffer rather than being immediately copied to application memory, avoiding unnecessary CPU intervention and memory bandwidth usage.
2Ease of operation
If receive buffers are allocated for all possible messages, then message delivery is straightforward, but memory usage increases significantly
Solution Approach 1:
The patent segments the message handling process into two distinct paths: matched messages (with pre-allocated buffers) and unexpected messages (without pre-allocated buffers). This segmentation allows the system to allocate memory resources dynamically based on actual message needs rather than pre-allocating for all possible scenarios, significantly reducing memory usage while maintaining ease of operation for expected messages.
3Adaptability or versatility
If tag matching is performed by the CPU, then message routing is flexible, but processing speed decreases
Solution Approach 1:
The patent extracts the tag matching operation from the CPU and implements it in hardware at the network interface card (NIC). The NIC performs tag comparison between incoming messages and posted receive operations, and manages unexpected message buffers independently. This extraction allows the CPU to focus on higher-level application logic while the hardware handles the time-critical tag matching, significantly improving processing speed while maintaining routing flexibility through the tag-matching protocol.
Data Source
AI summary
Examples described herein relate to a network interface device performing offloaded tag matching operation to support both one or more eager transactions and one or more rendezvous transactions using a tag-matching protocol. In some examples, the tag matching operation is offloaded from a server to the network interface device. In some examples, the network interface device is to receive messages from one or more senders, wherein the messages comprise tags and select one or more of the messages to write into a buffer based on matching on sender and/or tag.