Network I/O Packet Routing for Direct CPU Cache Access

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Solution Overview

Problem

Current methods for input/output transfer in network devices are inefficient due to limited cache resources and lack of selective data transmission to processing units, leading to bottlenecks and reduced efficiency, especially in high packet arrival rates.

Innovation Solution

A system and method for selectively transferring packets or packet portions to a processing unit based on attributes, allowing direct access to cache or registers while storing others in main memory, dynamically adjusting cache capacity and bandwidth for efficient processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional interrupt-driven I/O processing is used in network devices, then device compatibility is maintained, but processing efficiency deteriorates due to CPU overhead and context switching

Engineering Contradiction:
ImproveI/O processing efficiencyVSAvoidCPU overhead
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent replaces the traditional interrupt-driven mechanical control system with a polling-based system that uses dedicated I/O processing threads. Instead of relying on hardware interrupts to trigger processing, the system actively polls I/O queues at predetermined intervals, eliminating the need for context switching and interrupt handling overhead while maintaining device compatibility through standard queue interfaces

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent introduces an intermediary polling mechanism that acts as a mediator between the network interface card and the CPU. The polling thread continuously checks the I/O queue status and processes packets when available, serving as an intermediate layer that eliminates direct interrupt dependencies and reduces CPU involvement in I/O operations

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If packet buffering is implemented in network devices, then data loss is prevented, but memory consumption increases

Engineering Contradiction:
Improvedata loss preventionVSAvoidmemory consumption
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent dynamically adjusts buffer allocation parameters based on network traffic conditions and device capabilities. Buffer sizes are optimized to hold only the minimum necessary packets for maintaining reliability, and buffer management policies are adapted to balance data loss prevention with memory conservation through parameter tuning

Inventive Principle:
Principle #35Parameter changes

3Productivity

If context switching is used for I/O processing, then multi-threaded processing is achieved, but processing speed deteriorates due to switching overhead

Engineering Contradiction:
Improveprocessing speedVSAvoidcontext switching overhead
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent merges I/O processing functionality into dedicated kernel threads that run continuously without requiring context switches. Multiple I/O queues are processed by separate threads that maintain their own execution context, eliminating the need for frequent context switching while achieving parallel processing through thread consolidation rather than interrupt-based multi-tasking

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP4248590B1Method and system for efficient input/output transfer in network devices
Publication Date: 2026.05.20 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
  • EP4248590B1 patent drawingFigure 1A
  • EP4248590B1 patent drawingFigure 1B
  • EP4248590B1 patent drawingFigure 1C

AI summary

Methods and systems for selective direct access to a processing unit of a network device are described. A network interface of the network device receives packets of a flow. The network interface determines based on attributes of the packets that the packets are to be directly sent to the processing unit. In response to determining that the packets are to be directly sent to the processing unit, they are directly sent to the processing unit for processing.