Network System Latency Hiding via Parallel Memory Channels
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Solution Overview
Problem
Network systems face challenges in hiding system latencies due to constraints such as memory access latency, bridge or switch-induced hardware latency, and IOMMU translation table limitations, which degrade network performance and scalability.
Innovation Solution
The network system employs a protocol with relaxed ordering, independent and parallel data movement across multiple memory access channels, split transaction models, and maximized IOMMU locality to reduce latency, along with dedicated resources and reordering mechanisms for efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory access channels are used for parallel data movement, then network throughput is improved, but system complexity increases
Solution Approach 1:
The system divides memory access operations into multiple independent channels, each capable of parallel data movement. This segmentation allows the system to achieve higher throughput by distributing data transfer across multiple paths while maintaining manageable complexity through modular channel design.
Solution Approach 2:
The patent introduces parallelism across multiple memory access channels, adding a dimensional aspect to data movement. Instead of single-channel sequential access, the system utilizes multiple channels operating in parallel, effectively transforming the data transfer approach from one-dimensional to multi-dimensional operation.
2Loss of time
If relaxed ordering protocol is implemented, then latency is reduced, but data integrity constraints become more difficult to maintain
Solution Approach 1:
The system performs reordering operations in advance using reorder buffers before data is finally consumed. By anticipating and correcting out-of-order arrivals beforehand, the system can use relaxed ordering during data movement to reduce latency while ensuring data integrity is maintained when needed.
Solution Approach 2:
Reorder buffers act as intermediary structures between the parallel memory access channels and the data consumption logic. These buffers temporarily hold data that arrives out of order and release it in the correct sequence, mediating between the relaxed ordering protocol and the integrity requirements.
3Loss of time
If IOMMU locality is maximized, then translation overhead is reduced, but memory access patterns become more constrained
Solution Approach 1:
The system changes the parameters of IOMMU operation by maximizing locality, which means organizing memory translations to access the same translation table entries repeatedly. This parameter change reduces translation overhead by keeping relevant translation data in faster access locations, though it requires more structured memory access patterns.
Data Source
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AI summary
A method for addressing system latency within a network system which includes providing a network interface and moving data within each of the plurality of memory access channels independently and in parallel to and from a memory system so that one or more of the plurality of memory access channels operate efficiently in the presence of arbitrary memory latencies across multiple requests is disclosed. The network interface includes a plurality of memory access channels.