Network Linking Device Interrupt Co-Processor for Server Performance
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Solution Overview
Problem
The existing methods for asserting interrupt signals in network linking devices, such as packet-based, time-based, and hybrid manners, lead to inefficient resource utilization in microprocessors, particularly in high-throughput scenarios, causing performance deterioration and potential hang-ups in servers with multiple network interface cards.
Innovation Solution
A network linking device with a media access controller (MAC), a buffer, and a feature value evaluator that dynamically asserts an interrupt signal based on specific conditions within the data packet, such as destination address, data type, or protocol content, ensuring proper timing and resource management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If packet-based interrupt assertion is used, then data packets can be timely picked up by the operating system and memory resource is efficiently released, but when data packet throughput is high, the microprocessor operation resource is highly occupied by the network linking device, adversely affecting system performance
Solution Approach 1:
The patent introduces an interrupt co-processor as an intermediary component between the network interface card and the microprocessor. The co-processor handles interrupt signal generation and initial packet processing, acting as a mediator that offloads work from the main microprocessor. This allows the microprocessor to focus on higher-level tasks while the co-processor manages interrupt handling and packet filtering, thus improving system performance while maintaining efficient data packet transfer.
Solution Approach 2:
The interrupt co-processor is designed to autonomously perform interrupt assertion decisions based on pre-configured rules and packet features. It independently evaluates packets, determines interrupt timing, and generates interrupt signals without requiring continuous microprocessor intervention. This self-service capability reduces the microprocessor's resource occupation while maintaining timely packet transfer efficiency.
2Reliability
If time-based interrupt assertion is used, then the microprocessor operation resource is not highly occupied, but data packets must wait much longer to be transferred to the operating system, reducing transfer efficiency
Solution Approach 1:
The interrupt co-processor dynamically adjusts interrupt assertion timing based on real-time packet analysis and configured policies. Instead of fixed time-based intervals, the system dynamically determines when to assert interrupts based on packet characteristics, throughput conditions, and priority levels. This dynamic approach optimizes the balance between microprocessor resource occupation and data packet transfer efficiency under varying workloads.
Solution Approach 2:
The system changes the parameter of interrupt timing from static (time-based) to conditional (feature-based). The interrupt co-processor evaluates packet features such as type, size, and priority to dynamically adjust when interrupts are asserted. This parameter change allows the system to respond adaptively to different traffic conditions, improving transfer efficiency without excessively occupying the microprocessor.
3Productivity
If hybrid interrupt assertion is used, then interrupt timing can be regulated according to data packet throughput, but it is hard to control the timing for the MAC to assert the hardware interrupt signal since it is hard to predict data packet throughput
Solution Approach 1:
The interrupt co-processor is pre-configured with interrupt assertion rules, policies, and evaluation criteria before system operation. These preliminary configurations include thresholds, priority levels, and packet feature weights that guide interrupt timing decisions. By establishing these rules in advance, the system eliminates the need for complex real-time predictions of data packet throughput, simplifying control while maintaining optimized interrupt timing.
Solution Approach 2:
The interrupt co-processor implements feedback mechanisms that monitor actual packet throughput and interrupt handling performance. Based on this feedback, the system dynamically adjusts interrupt assertion strategies within the pre-configured rule framework. This feedback loop allows the system to adapt to changing throughput conditions without requiring complex predictive algorithms, reducing control complexity while maintaining productivity optimization.
Data Source
AI summary
A network linking device in communication with a computer host and an external network is disclosed. The network linking device includes a media access controller (MAC), a buffer and a feature value evaluator. The MAC in communication with the external network receives a data packet from the external network, and stores the data packet in the buffer in communication therewith. The feature value evaluator in communication with the buffer determines whether the data packet complies with a transfer condition according to a feature value included in the data packet, and actuates the MAC to assert an interrupt signal to the computer host when the feature value indicates the data packet complies with the transfer condition. A method for transferring a data packet between a computer host and an external network is also disclosed.