Network Memory Load Management via Cross-Appliance Status Exchange

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Solution Overview

Problem

Current network memory systems face inefficiencies due to slow data retrieval from slower memory, leading to appliance overload and network traffic bottlenecks, as they struggle to quickly process instructions and manage data access between faster and slower memory levels.

Innovation Solution

A system that includes a communication interface and processor to receive status messages and data packets, estimating data location and activity levels to optimize data retrieval by limiting slower memory access, generating instructions for faster data transfer, and transmitting data directly when slower memory is overloaded, thereby reducing network traffic and improving data access efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If data is retrieved from slower memory, then data storage capacity is improved, but data retrieval speed deteriorates

Engineering Contradiction:
Improvedata storage capacityVSAvoiddata retrieval speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The system pre-loads frequently accessed data from slower memory to faster memory in advance, so that when data is needed, it is already available in the faster memory, eliminating the speed penalty of slow memory retrieval

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

A cache memory system acts as an intermediary between the faster memory and slower memory, buffering data transfers and providing fast access to frequently used data while maintaining access to the larger slower memory capacity

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If data access to slower memory is increased, then data availability is improved, but appliance load increases

Engineering Contradiction:
Improvedata availabilityVSAvoidappliance load
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The system implements differential caching strategies where different types of data receive different levels of caching based on their access patterns and importance, reducing the overall load on slower memory while maintaining availability for critical data

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system caches more data in faster memory than strictly necessary (excessive action), pre-loading data that may be needed soon, thereby reducing slower memory access and appliance load while maintaining high data availability

Inventive Principle:
Principle #16Partial or excessive action

3Speed

If data is cached in faster memory, then data access speed is improved, but memory management complexity increases

Engineering Contradiction:
Improvedata access speedVSAvoidmemory management complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The caching system uses self-organizing algorithms that automatically track data access patterns and manage cache contents without external intervention, maintaining fast data access while keeping management operations autonomous and simplified

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system dynamically adjusts cache parameters such as cache size, replacement policies, and pre-loading thresholds based on observed workload characteristics, optimizing data access speed while adapting management complexity to actual system needs

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS7945736B2Dynamic load management of network memory
Publication Date: 2011.05.17 HEWLETT PACKARD ENTERPRISE DEV LP
  • US7945736B2 patent drawing
  • US7945736B2 patent drawing
  • US7945736B2 patent drawing

AI summary

A system for managing network memory comprises a communication interface and a processor. The communication interface receives a status message from another appliance. The status message indicates an activity level of a faster memory and a slower memory associated with the other appliance. The communication interface also receives a data packet. The processor processes the status message to determine the activity level of the faster memory and the slower memory. The processor also processes the data packet to identify any matching data in the other appliance and estimate whether the matching data is stored in the faster memory based on the activity level. Based on the estimate, the processor determines whether to generate an instruction to retrieve the matching data.