Network Device Packet Demultiplexing for High-Bandwidth Bus Efficiency

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Solution Overview

Problem

Designing a parallel data bus within a network device for high bandwidth network interfaces is challenging due to efficiency declines when data packet lengths are not integer multiples of the data bus width, particularly affecting small data packets.

Innovation Solution

The network device splits incoming data packets onto multiple independent data paths using a demultiplexer and aggregates them back using a multiplexer, maintaining line rate for high data transmission rates by packing packets back-to-back and alternating them across these paths.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the parallel data bus width is increased to support high bandwidth network interfaces, then the data transmission rate is improved, but the data bus efficiency deteriorates when data packet lengths are not integer multiples of the data bus width

Engineering Contradiction:
Improvedata transmission rateVSAvoiddata bus efficiency
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The patent segments the data bus into multiple independent data paths by introducing a demultiplexer that divides incoming data packets onto separate paths. This allows the system to maintain high bandwidth capability while improving efficiency for packets that are not integer multiples of the original bus width, as each segment can handle packets independently without wasting bandwidth.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a single-dimensional data bus to a multi-dimensional data path structure by using multiple parallel paths. This dimensional expansion allows the system to accommodate variable packet lengths more efficiently while maintaining high transmission rates, as packets can be distributed across multiple dimensions (paths) rather than being constrained to a single fixed-width bus.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Power

If the parallel data bus width is increased to support high bandwidth network interfaces, then the internal bandwidth for buffering and processing is improved, but the device complexity increases

Engineering Contradiction:
Improveinternal bandwidthVSAvoiddata bus structure complexity
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The patent segments the data bus functionality into separate data paths managed by demultiplexing and multiplexing circuits. This segmentation allows the system to achieve higher internal bandwidth through multiple parallel paths while managing complexity by using standardized demultiplexing and multiplexing operations rather than requiring a completely new complex data bus architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent makes the demultiplexer and multiplexer circuits universal components that can handle multiple packet sizes and bandwidth requirements. These circuits serve multiple functions: they can demultiplex packets onto different paths, multiplex packets from paths back to the data bus, and adapt to various packet lengths, thereby reducing the need for specialized hardware for each function.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250240187A1Network Device with High Bandwidth Packet Processing Capabilities
Publication Date: 2025.07.24 ARISTA NETWORKS INC
  • US20250240187A1 patent drawing
  • US20250240187A1 patent drawing
  • US20250240187A1 patent drawing

AI summary

A method of operating a network device is provided. The method can include obtaining incoming data packets, conveying the incoming data packets through a parallel data bus, and using a demultiplexer to split the incoming data packets being conveyed through the parallel data bus onto a plurality of separate independent data paths within the network device. The method can further include using a multiplexer to aggregate or merge data packets from the plurality of data paths onto an egress parallel data bus.