Network Packet Processing Using Dual Memory Latency
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Solution Overview
Problem
Conventional network processing units (NPUs) face performance limitations due to the high access latency of dynamic random access memory (DRAM), which degrades packet forwarding processing efficiency.
Innovation Solution
The implementation of a network packet processing apparatus that utilizes a second memory with lower access latency, such as static random access memory (SRAM), in conjunction with a first memory (DRAM) and a direct memory access (DMA) controller, to store partial packet content. This allows the NPU to perform packet pre-processing more efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM is used to store network packets, then large capacity is achieved, but access latency increases significantly
Solution Approach 1:
The patent divides the memory system into two segments: DRAM for bulk packet storage and SRAM for pre-processing data storage. The DMA controller segments the packet data writing operation, storing complete packets in DRAM while simultaneously copying pre-processing required data to SRAM. This segmentation allows the system to leverage both memory types' strengths.
Solution Approach 2:
The patent implements preliminary action by pre-copying packet data from DRAM to SRAM while the packet is being received and stored. The DMA controller performs this data transfer in advance of the NPU's processing needs, ensuring that when the NPU requires packet data for pre-processing, the data is already available in the faster SRAM memory.
2Ease of operation
If NPU performs packet pre-processing from DRAM, then packet processing is enabled, but overall forwarding efficiency is degraded
Solution Approach 1:
The patent introduces SRAM as an intermediary memory between DRAM and the NPU. Instead of the NPU directly accessing DRAM for pre-processing operations, it accesses SRAM which contains pre-copied packet data. This intermediary layer eliminates the bottleneck of direct DRAM access while maintaining the NPU's pre-processing capability.
Solution Approach 2:
The DMA controller performs preliminary data preparation by copying packet contents to SRAM before the NPU needs to access them for pre-processing. This advance preparation ensures that when the NPU initiates pre-processing operations, the required data is already resident in the faster SRAM memory, eliminating wait states and improving throughput.
Data Source
AI summary
A network packet processing apparatus includes a first memory, a second memory, a direct memory access (DMA) controller, and a network processing unit (NPU). Access latency of the second memory is lower than access latency of the first memory. The DMA controller is used to write a network packet into the first memory, and write a partial packet content of the network packet into the second memory. The NPU reads the partial packet content from the second memory, and performs packet pre-processing of the network packet according to the partial packet content.