Network Packet Processing Pipeline With Textual Specification Synthesis
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Solution Overview
Problem
The development of network packet processors requires expertise from multiple fields, making the process time-consuming and expensive, and there is a need for rapid development to improve timeliness and quality.
Innovation Solution
A pipeline processing network packets is generated from a textual language specification, including a look-ahead stage, operation stage, insert/remove stage, and interleave stage, which synchronizes, modifies, and ensures proper interleaving of packet fields, allowing for efficient hardware implementation in programmable logic devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a hardware implementation of a network packet processor is developed using traditional methods requiring multiple fields of expertise, then the implementation can be created, but the development process becomes time-consuming and expensive
Solution Approach 1:
The patent uses a protocol specification (textual description) as a template or copy that automatically generates the hardware implementation code. Instead of manually creating complex hardware designs requiring multiple expertise areas, the system copies the protocol specification into a hardware implementation through automatic synthesis, eliminating the need for specialized hardware design skills while maintaining implementation quality
Solution Approach 2:
The patent introduces an automatic synthesis tool as an intermediary between the protocol specification and the hardware implementation. This mediator automatically translates high-level protocol descriptions into detailed hardware code, bridging the gap between protocol design and hardware implementation without requiring direct expertise in both fields by the same designer
2Reliability
If rapid iterations of network packet processor implementation are performed to address deficiencies, then the quality and timeliness improve, but this requires the hardware implementation to be generated quickly from protocol specifications
Solution Approach 1:
The patent performs preliminary actions by automatically generating the complete hardware implementation code from the protocol specification in advance. This allows protocol designers to immediately simulate and test the generated hardware without waiting for manual implementation, enabling rapid identification and correction of deficiencies through quick iteration cycles
Solution Approach 2:
The automatic synthesis process creates a copy of the protocol specification in hardware implementation form, which can be rapidly simulated and tested. This copying mechanism enables quick iteration because any changes to the protocol specification automatically generate updated hardware code, allowing rapid verification of improvements without manual re-implementation
Data Source
AI summary
A pipeline is provided for processing network packets. The pipeline includes a look-ahead stage, an operation stage, an insert/remove stage, and an interleave stage. The look-ahead stage synchronizes two or more fields of a network packet. The operation stage modifies one or more of the fields of the network packet. The operation stage may modify state data and the fields of the network packet as a function of the state data and the fields. The insert/remove stage performs data insertion and removal at one or more fields of the network packet. The interleave stage ensures that the modified network packet follows rules for interleaving network packets. The look-ahead, operation, insert/remove, and interleave stages are generated from a textual language specification of the processing of the network packets by the pipeline.