Network Packet Receiving Apparatus with Shared Descriptor Buffer
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Solution Overview
Problem
In large server systems, network packet transmission leads to inefficient use of hardware resources as multiple operation systems require separate hardware configurations for different channels, resulting in resource waste and processor overload due to frequent interrupts.
Innovation Solution
A network packet receiving apparatus with multiple packet queues, a credit allocation circuit, and a credit management circuit that calculates packet amounts, controls descriptor credits, and enables direct memory access (DMA) operations by assigning descriptors from a shared buffer, optimizing resource usage and reducing interrupts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple hardware configurations are used for different channels, then packet processing capability is improved, but hardware resource utilization deteriorates
Solution Approach 1:
The patent merges multiple channel-specific hardware configurations into a single shared hardware resource pool. Multiple packet queues corresponding to different channels share common descriptor buffers and credit management circuits, eliminating redundant hardware while maintaining the ability to process packets from multiple channels simultaneously through logical multiplexing.
Solution Approach 2:
The shared hardware resources are designed to serve multiple functions and multiple channels universally. The descriptor buffer and credit management circuit can dynamically allocate resources to any active channel based on current packet processing needs, making the hardware universal rather than dedicated to specific channels.
2Adaptability or versatility
If separate hardware configurations are allocated to different channels, then channel processing independence is improved, but device complexity increases
Solution Approach 1:
The system segments channel processing into logical packet queues that maintain independence through separate queue management, while sharing physical hardware resources. Each channel's packet queue operates independently with its own credit allocation, but the underlying hardware (descriptor buffers, DMA circuits) is shared, reducing complexity while preserving functional independence.
Solution Approach 2:
The credit management circuit acts as an intermediary layer between independent channel requirements and shared hardware resources. It mediates resource allocation by calculating packet amounts, managing descriptor credits, and coordinating access to shared buffers, thereby maintaining channel independence without requiring separate hardware configurations.
3Reliability
If multiple descriptor buffers are used for different channels, then channel isolation is improved, but memory resource utilization deteriorates
Solution Approach 1:
Multiple channel-specific descriptor buffers are merged into a single shared descriptor buffer. The buffer is logically divided into multiple packet queues, each corresponding to a different channel. This merging reduces total memory consumption while maintaining channel isolation through logical separation and credit-based access control.
Solution Approach 2:
The system changes the parameter of descriptor buffer allocation from fixed per-channel allocation to dynamic shared allocation. The credit management circuit dynamically adjusts the effective buffer size available to each channel based on current packet processing demands, optimizing memory utilization while maintaining channel isolation through credit limits.
Data Source
AI summary
A network packet receiving device that includes packet queues, a credit allocation circuit and a credit management circuit is provided. Each of the packet queues corresponds to a packet transmission channel and receives packets. The credit allocation circuit calculates packet amount of each of the packet queues to control the descriptor credit of each of the packet queues within a credit range. The credit management circuit points each of public entries of a public link list to one of descriptors in a single descriptor buffer. The credit management circuit further receives a credit requesting command from the packet queues to assign the descriptors to the packet queues through the public entries under the condition that the descriptor credit is within a credit range such that a DMA circuit performs a DMA operation on the packets according to the descriptors.