Network Parser Repeat Mode for Packet Parsing Speed

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Solution Overview

Problem

Current network processors face inefficiencies in data packet parsing due to high power consumption and inflexibility, particularly in multi-gigabit networks, as they require increased clock frequencies and more powerful hardware, leading to financial and ecological drawbacks.

Innovation Solution

A network processor with a rules repository and a parser that operates in both normal and repeat modes, dynamically switching between them based on analysis results, allowing for efficient execution of rules without the need for additional clock cycles, thereby reducing power consumption and increasing parsing performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the clock frequency of the parser is increased to improve parsing speed, then the parsing performance is improved, but the power dissipation increases

Engineering Contradiction:
Improveparsing speedVSAvoidpower dissipation
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The parser operation is segmented into two distinct modes: normal operation mode and repeat operation mode. This segmentation allows the system to optimize for different operational requirements, using the appropriate mode based on the parsing context, thereby improving overall efficiency without continuously operating at high power consumption levels

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The parser dynamically switches between normal operation mode and repeat operation mode based on runtime conditions. This dynamic adaptation allows the system to adjust its operational characteristics in real-time, maintaining high parsing speed when needed while reducing power dissipation during repetitive operations that don't require full instruction loading cycles

Inventive Principle:
Principle #15Dynamics

2Productivity

If ASICs are used to improve parsing efficiency and speed, then the parsing performance is improved, but the flexibility and adaptability are reduced

Engineering Contradiction:
Improveparsing efficiencyVSAvoidflexibility
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The network processor is designed with a universal parser that can operate in multiple modes (normal and repeat operation modes) and execute different types of instructions. This multi-functionality allows a single device to adapt to various parsing requirements while maintaining high efficiency, eliminating the need for separate specialized hardware for different parsing scenarios

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If GPPs are used to improve flexibility, then the adaptability is improved, but the parsing speed is reduced

Engineering Contradiction:
ImproveflexibilityVSAvoidparsing speed
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The parser implements dynamic operation modes that allow it to switch between normal operation (with full instruction loading) and repeat operation (without reloading instructions). This dynamic behavior enables the system to maintain the flexibility of GPPs while achieving parsing speeds comparable to or exceeding specialized hardware by optimizing the instruction execution cycle based on runtime conditions

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8867395B2Accelerating data packet parsing
Publication Date: 2014.10.21 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US8867395B2 patent drawing
  • US8867395B2 patent drawing
  • US8867395B2 patent drawing

AI summary

Mechanisms are provided for a network processor comprising a parser, the parser being operable to work in normal operation mode or in repeat operation mode, the parser in normal operation mode loading and executing at least one rule in a first and a second working cycle respectively, the parser in repeat operation mode being operable to repeatedly execute a repeat-instruction, the execution of each repeat corresponding to one working cycle.