Network Apparatus Pipelining Resource Sharing
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Solution Overview
Problem
The parallel pipelining architecture in network packet processing devices faces challenges with increasing resource consumption, such as table lookup bandwidth and power consumption, which outpaces the development of semiconductor technology, making it difficult to implement high-performance chip designs that meet the growing processing demands.
Innovation Solution
A data processing method is introduced that utilizes two circuit sets within a network apparatus, where processing circuits share intermediate data and instructions based on identical fields in packet headers, allowing one circuit set to remain idle and reducing resource utilization, thereby decreasing power consumption and improving processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple parallel pipelines are used to process network packets, then packet processing rate is improved, but resource consumption (table lookup bandwidth, power consumption) increases proportionally
Solution Approach 1:
The patent merges multiple parallel pipelines into a single unified pipeline that processes packets sequentially. The single pipeline shares processing resources across multiple packets, eliminating the need for each pipeline to have dedicated table lookup units and other resources. This combining approach maintains high packet processing rates while significantly reducing power consumption and resource usage.
Solution Approach 2:
The single pipeline is designed to be universal and multi-functional, capable of processing different packets and handling various network protocols. The processing circuits within the single pipeline can be dynamically allocated and reused for different packets, making the resource highly efficient and eliminating the waste of having dedicated resources in multiple parallel pipelines.
2Productivity
If multiple parallel pipelines are used to process network packets, then packet processing rate is improved, but table lookup bandwidth consumption increases proportionally
Solution Approach 1:
The patent combines multiple table lookup units into a single shared table lookup resource that serves the entire pipeline. This single table lookup unit processes lookup requests from different packets sequentially, dramatically reducing the total table lookup bandwidth consumption compared to having dedicated table lookup units in each parallel pipeline, while still maintaining high overall processing throughput.
Solution Approach 2:
The single pipeline ensures continuous processing of packets through efficient resource utilization. The shared table lookup unit continuously serves different packets without idle time, and the pipeline maintains a steady flow of packet processing, ensuring that the single table lookup resource is fully utilized and no bandwidth is wasted.
3Productivity
If multiple parallel pipelines are used to process network packets, then packet processing rate is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple parallel pipelines into a single pipeline architecture, which significantly simplifies chip implementation. Instead of designing and integrating multiple independent pipeline units with their own resources, the single pipeline approach reduces the overall device complexity while maintaining high processing throughput through efficient resource sharing and sequential processing.
Data Source
AI summary
A data processing method and a related device are provided. The method includes receiving, by the i.sup.th processing circuit in a first circuit set, a first packet header and data D.sub.(1, i-1), obtaining data D'.sub.(1, i) based on a first field in the first packet header, and sending the first packet header and data D.sub.(1, i) to the (i+1).sup.th processing circuit in the first circuit set, where the data D.sub.(1, i) is obtained based on the data D.sub.(1, i-1) and the data D'.sub.(1, i). The method also includes sending, by the i.sup.th processing circuit in the first circuit set, the data D.sub.(1, i) to the (i+1).sup.th processing circuit in a second circuit set and sending, by the i.sup.th processing circuit in the second circuit set, a second packet header to the (i+1).sup.th processing circuit in the second circuit set.