Network Port Frame Scheduling to Prevent Switch Buffer Overflow
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Solution Overview
Problem
In asynchronous control networks, synchronizing the transmission of frames from asynchronously operating sensors to prevent buffer overflow in switches, which requires complex and costly buffer design to handle potential simultaneous frame arrivals.
Innovation Solution
Assigning unique time slots to each sensor based on a switch-associated cycle time, determined by an offset value and port number, allowing sensors to transmit frames without overlapping, thus simplifying network design and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If asynchronous sensors transmit frames independently without coordination, then each sensor can operate autonomously with simple design, but buffer overflow occurs in switches due to simultaneous frame arrivals
Solution Approach 1:
The patent implements periodic time slots within a switch-associated cycle time, where each sensor is assigned specific time slots for frame transmission. This periodic structure ensures that sensors transmit frames in an organized sequence rather than randomly, preventing buffer overflow while maintaining autonomous operation. The cycle time and offset values create a repeating pattern that coordinates transmissions across all sensors.
Solution Approach 2:
The patent assigns time slots to sensors in advance based on their port numbers and offset values before actual frame transmission occurs. This preliminary assignment of transmission windows allows sensors to know exactly when they can transmit, eliminating the need for real-time negotiation or complex buffer management during operation, thus preventing buffer overflow proactively.
2Reliability
If large buffers are implemented in switches to handle simultaneous frame arrivals, then buffer overflow is prevented, but device complexity and cost increase
Solution Approach 1:
Instead of using large buffers to absorb random frame arrivals, the patent implements a periodic time slot structure where frame transmissions are naturally spaced out in time. This eliminates the need for large buffers because frames arrive in an organized sequence that matches the switch's processing capacity, significantly reducing buffer size requirements and device complexity.
Solution Approach 2:
The patent replaces the mechanical approach of using large physical buffers to handle traffic bursts with a temporal coordination mechanism. By assigning time slots based on port numbers and offset values, the system uses time-based control rather than space-based buffering, substituting a simpler control mechanism for complex hardware design.
3Reliability
If time slot assignment based on port numbers and offset values is implemented, then frame transmissions are synchronized without overlapping, but network protocol complexity increases
Solution Approach 1:
The patent uses simple parameter changes based on existing port numbers and offset values to determine time slot assignments. Each sensor calculates its transmission time slots by applying its assigned offset value to the switch-associated cycle time, creating a straightforward mathematical relationship that ensures non-overlapping transmissions without requiring complex protocol logic.
Solution Approach 2:
Sensors autonomously determine their own transmission time slots by using their assigned port numbers and offset values in conjunction with the switch-associated cycle time. This self-service approach allows each sensor to independently calculate when it should transmit without requiring complex centralized control or negotiation protocols, simplifying the overall network protocol while ensuring synchronized transmissions.
Data Source
AI summary
Examples disclosed herein relate generally to providing frames at a network port. Some examples relate to an apparatus. The apparatus may include a network port to directly couple the apparatus to a switch. The apparatus may also include a transmission logic to provide a frame at the network port at a time slot of a switch-associated cycle time. The transmission logic may provide the frame at the time slot at least partially responsive to an offset value and a port number. Related devices, systems and methods are also disclosed.