Network Processor Grid Architecture for High-Speed Traffic Handling
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Solution Overview
Problem
Current network processors in residential gateways become bottlenecks due to their inability to handle high volumes of traffic efficiently, particularly in supporting advanced applications and high-speed data services such as streaming video and real-time gaming.
Innovation Solution
A network processor architecture that includes a control processor, external and internal memory, ingress/egress interfaces, a dispatcher/reorderer, packet processor grid, queue manager, and accelerators, which implement load balancing and packet reordering using linked lists and multiple threads to manage packet processing and switching, while offloading tasks to dedicated hardware for increased performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional network processor architecture is used, then device complexity is reduced, but processing capacity and productivity deteriorate due to inability to handle high volumes of traffic at wireline speeds
Solution Approach 1:
The network processor is divided into multiple packet processors (PP0, PP1, PP2, etc.) organized in a grid, each capable of independent packet processing. This segmentation allows parallel processing of multiple packets simultaneously, dramatically increasing throughput and processing capacity while maintaining manageable complexity through modular design
Solution Approach 2:
The patent introduces a two-dimensional packet processor grid architecture where packet processors are arranged in rows and columns. This dimensional expansion allows for scalable parallel processing - adding more packet processors along either dimension increases capacity linearly, providing a systematic approach to handling high-volume traffic without proportionally increasing overall system complexity
2Productivity
If multiple packet processors are used to increase processing capacity, then productivity improves, but packet ordering becomes difficult to maintain
Solution Approach 1:
A reorder buffer is introduced as an intermediary component between the parallel packet processors and the output interface. Each packet processor writes processed packets to the reorder buffer with associated metadata including original packet identifiers and sequence information. The reorder buffer sorts packets based on this metadata before forwarding them to the output, ensuring correct packet ordering is restored after parallel processing
Solution Approach 2:
The system performs preliminary tagging of packets with sequence identifiers and metadata before they are distributed to multiple packet processors. This preliminary action enables the reorder buffer to efficiently restore correct packet sequence without requiring complex synchronization mechanisms during processing, as the ordering information is already embedded in the packet descriptors
3Productivity
If load balancing is implemented across multiple packet processors, then processing efficiency improves, but system complexity increases due to need for coordination and packet reordering
Solution Approach 1:
Each packet processor independently performs load-balanced packet processing using locally available resources and pre-computed distribution algorithms. The packet processors autonomously select packets from the input queue based on hash functions or round-robin schemes without requiring real-time coordination with other packet processors, eliminating the need for complex inter-processor communication and synchronization mechanisms
Data Source
AI summary
The present disclosure is directed to a network processor for processing high volumes of traffic provided by todays access networks at (or near) wireline speeds. The network process can be implemented within a residential gateway to perform, among other functions, routing to deliver high speed data services (e.g., data services with rates up to 10 Gbit/s) from a wide area network (WAN) to end user devices in a local area network (LAN).