Network Processor Parsing Logic External Coprocessor Interface
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Solution Overview
Problem
Existing network processor systems face challenges in efficiently connecting external coprocessors due to area limitations and the need for flexible bandwidth support, as they often require different processing architectures and large logic arrays for tasks like packet classification and filtering, which cannot be handled by the network processor chip alone.
Innovation Solution
The implementation of first communication protocol ports that support 'M' minimum size packet data path traffic on 'N' lanes at 'S' Gbps, with additional lanes for different communication protocol units at 's' Gbps, allowing for flexible access to an external coprocessor using parsing logic that sends requests and receives responses, adhering to the equation N×S/M=<n×s/m, thereby optimizing the connection and reuse of existing control/management bidirectional serial lanes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If packet classification and filtering functions are externalized to a coprocessor, then the network processor chip area is reduced, but the device complexity increases due to the need for additional external components and interfaces
Solution Approach 1:
The patent extracts packet classification and filtering functions from the network processor chip to an external coprocessor. The TCAM and associated logic are moved outside the main chip, reducing its area while maintaining the functionality through the external coprocessor that communicates via standardized interfaces.
Solution Approach 2:
The patent introduces a standardized interface as an intermediary between the network processor chip and the external coprocessor. This interface layer manages communication protocols and data exchange, allowing the system to handle complexity externally while presenting a simplified interface to the main processor.
2Reliability
If a dedicated interface is provided for coprocessor communication, then the communication reliability is improved, but the device complexity and silicon area increase
Solution Approach 1:
The patent designs a universal interface that can handle multiple communication functions including packet classification requests, filtering operations, and data exchanges. This single multi-functional interface replaces what would otherwise require multiple dedicated interfaces, reducing overall complexity while maintaining reliable communication.
3Productivity
If the parser hands off functions to an external coprocessor, then the network processor productivity is improved by offloading complex tasks, but the loss of time increases due to communication overhead between the parser and coprocessor
Solution Approach 1:
The patent implements preliminary action by having the parser prepare and queue classification requests before they are fully processed. The interface is designed to accept and buffer requests in advance, allowing the coprocessor to process them efficiently without causing delays to the main packet processing flow.
Solution Approach 2:
The patent ensures continuous useful action by maintaining a pipelined communication interface where requests are continuously sent to and processed by the coprocessor. The interface is designed to keep both the parser and coprocessor continuously engaged, minimizing idle time and maintaining high throughput for classification operations.
Data Source
AI summary
A network processor includes first communication protocol ports that each support ‘M’ minimum size packet data path traffic on ‘N’ lanes at ‘S’ Gigabits per second (Gbps) and traffic with different communication protocol units on ‘n’ additional lanes at ‘s’ Gbps. The first communication protocol ports support access to an external coprocessor using parsing logic located in each of the first communication protocol ports. The parsing logic, during a parsing period, is configured to send a request to the external coprocessor at reception of a ‘M’ size packet and to receive a response from the external coprocessor. The parsing logic sends a request maximum ‘m’ size byte word to the external coprocessor on one of the additional lanes and receives a response maximum ‘m’ size byte word from the external coprocessor on the one of the additional lanes while complying with the equation N×S/M=<n×s/m.