Network Processor Silicon Area Reduction via External Memory Frame Storage
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Solution Overview
Problem
In pipelined network processors, stopping the transmission of priority flow-controlled frames without interrupting other flows is challenging due to the pipeline's multi-stage nature, leading to potential buffer overflows and inefficiencies in silicon area, power, and speed.
Innovation Solution
Employing external memory to store paused frames, allowing the network processor to halt transmission of priority flow-controlled frames without affecting other flows, thereby addressing the timing violations and optimizing resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single multi-level pipeline is used to handle all priority queues, then device complexity is reduced, but it becomes difficult to pause one priority queue without pausing the entire pipeline
Solution Approach 1:
The patent segments the single pipeline into multiple independent priority queues, each with its own control logic. This allows individual queues to be paused or resumed independently while maintaining the overall pipeline structure, resolving the contradiction between simplicity and adaptability.
Solution Approach 2:
The patent introduces intermediary structures (such as queue management units and control registers) that mediate between the control logic and the pipeline stages. These intermediaries enable selective pausing of specific priority queues without affecting others, while keeping the pipeline architecture relatively simple.
2Reliability
If internal FIFOs and separate pipelines are used to handle paused frames, then priority flow control reliability is improved, but silicon area increases
Solution Approach 1:
The patent merges the functions of multiple separate pipelines and FIFOs into a single shared pipeline structure with logical separation of priority queues. This combining approach maintains the reliability of priority flow control through logical isolation while reducing the physical silicon area by eliminating redundant hardware structures.
Solution Approach 2:
The patent creates a universal pipeline structure that can handle multiple priority queues simultaneously. This multi-functional pipeline serves the role of what would otherwise require multiple dedicated pipelines, reducing silicon area while maintaining the ability to provide reliable priority-based flow control for each queue independently.
3Reliability
If the entire pipeline is paused to stop transmission of a paused priority queue, then flow control reliability is improved, but processing speed of other flows decreases
Solution Approach 1:
The patent segments the pipeline into independently controllable priority queue channels. When one priority queue needs to be paused for flow control, only that specific channel is stopped while other channels continue processing at full speed. This segmentation enables reliable flow control for individual queues without impacting the productivity of other flows.
Solution Approach 2:
The patent applies local quality control by allowing different operational states (paused or active) for different priority queues within the same pipeline. Each queue can have its own pause/resume state independent of others, enabling flow control reliability for specific queues without reducing the processing speed of queues that are not paused.
Data Source
AI summary
In a pipelined network processor, a first stage in the pipeline is responsive to receipt of a pause indication from a third stage. The pause indication is associated with one of a plurality of ports and priority classes of frames advancing through the pipeline. The first stage asserts a hold indication to a second stage in response to the pause indication. The second stage is responsive to the hold indication by marking frames associated with the one of a plurality of ports and priority classes as they arrive from the pipeline at the second stage by returning them to the first stage interface instead of transmitting them to the third stage. The marked frames are stored in memory external to the network processor.