Network Processor Thread Abnormality Detection via Shared Memory Flag Bits

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Solution Overview

Problem

Current methods for detecting abnormalities in network processors are inefficient, relying on manual investigation and requiring external components like light-emitting diodes, which are impractical for high-frequency network processors, and existing forecasting methods are not suitable for complex service processing environments.

Innovation Solution

A method and system that adds abnormality detection operation code into the execution flow of each thread in a network processor, using a shared memory to set flag bits and a coprocessor to detect abnormalities based on timer expiration, allowing for timely and efficient failure detection without affecting forwarding performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If manual investigation is used to detect network processor abnormalities, then detection can be performed, but it consumes a lot of manpower and increases operation and maintenance cost

Engineering Contradiction:
Improveabnormality detection capabilityVSAvoidoperation and maintenance cost
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The network processor automatically detects its own abnormalities through embedded detection operation codes in the execution flow of each thread. The processor sets flag bits in shared memory when executing these codes, enabling self-diagnosis without external manual intervention, thus reducing operation and maintenance costs while maintaining detection capability.

Inventive Principle:
Principle #25Self-service

2Measurement precision

If external light-emitting diode is used for display, then program position can be displayed, but it is impossible due to extremely high running frequency of network processor and very fast update of program position

Engineering Contradiction:
Improveprogram position detectionVSAvoidprocessor running frequency
Core Design Contradiction:
Measurement precisionVSSpeed

Solution Approach 1:

The patent introduces shared memory as an intermediary between the network processor and the coprocessor. The processor writes detection results (flag bits) to the shared memory at its own high speed, and the coprocessor reads these results at its own pace, eliminating the speed mismatch problem that would make external display impossible.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

Instead of directly displaying the rapidly changing program position, the system creates a copy of the position information in flag bits within shared memory. This copied information can be read by the coprocessor without being affected by the processor's high running frequency, enabling accurate measurement.

Inventive Principle:
Principle #26Copying

3Reliability

If forecasting table is created in advance for crash probability, then crash forecasting can be performed, but it is difficult to apply to detecting crash abnormality of network processor due to complicated service processing

Engineering Contradiction:
Improvecrash forecasting capabilityVSAvoidapplicability to complex services
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The system performs preliminary action by embedding detection operation codes in the execution flow before any abnormality occurs. These codes automatically set flag bits in shared memory during normal execution, preparing the detection mechanism in advance without requiring pre-created forecasting tables, thus adapting to any service complexity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Instead of using a static forecasting table, the system employs dynamic detection where flag bits are continuously updated in shared memory based on the actual execution state of each thread. This dynamic approach adapts to complicated service processing by reflecting real-time processor status regardless of service complexity.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8977905B2Method and system for detecting abnormality of network processor
Publication Date: 2015.03.10 ZTE CORP
  • US8977905B2 patent drawing
  • US8977905B2 patent drawing
  • US8977905B2 patent drawing

AI summary

The disclosure discloses a method and a system for detecting an abnormality of a network processor. The method comprises the following steps: an abnormality detection operation code is added into an execution flow of each thread in a network processor, and the network processor sets a flag bit corresponding to a current thread in an abnormality protection flag data area in a shared memory to a first flag when executing the abnormality detection operation code in the current thread; and when a period of a timer is expire, a coprocessor detects all the flag bits in the abnormality protection flag data area in the shared memory, determines that a thread corresponding to a flag bit which is not the first flag is abnormal when detecting that not all the flag bits are the first flag, and sets all the flag bits to a second flag when detecting that all the flag bits are the first flag. Through the disclosure, the abnormality of a thread can be detected timely and efficiently, so that the failure detection capability of the network device using the network processor as a core unit at run time is improved without influencing the forwarding performance and service processing flow of the network processor.