Network Receiver Clock Bit Comparator for CAN Synchronization
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Solution Overview
Problem
In networks using distributed clock synchronization, such as the Controller Area Network (CAN), achieving accurate internal clock synchronization across a wide temperature range and long lifetime is challenging, especially when using fully integrated RC or LC oscillators without external components, as they often require low precision to minimize power and manufacturing costs, leading to potential decoding errors if not within specified tolerance limits.
Innovation Solution
A network receiver with an internal clock that includes a clock bit comparator and an adjustment signal generator to compare the length of received bit periods with internal clock intervals, generating a frequency adjustment signal to align the internal clock frequency with the received signal, thereby maintaining synchronization accuracy within the CAN specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a fully integrated RC or LC oscillator is used without external components, then manufacturing cost and device complexity are reduced, but clock accuracy deteriorates and may fall outside specified tolerance limits
Solution Approach 1:
The patent implements a feedback mechanism where the receiver monitors its own sampling accuracy by detecting bit errors or synchronization deviations, then adjusts the oscillator frequency accordingly. This closed-loop control allows the use of low-precision integrated oscillators while maintaining effective synchronization through continuous correction based on received signal quality.
Solution Approach 2:
The patent dynamically changes the oscillator frequency parameter based on measured synchronization performance. By adjusting the clock frequency in response to detected errors or drift, the system compensates for the inherent imprecision of integrated oscillators, allowing cost-effective RC or LC oscillators to achieve the required synchronization accuracy.
2Reliability
If multiple timing engines with different sampling frequencies are implemented, then reliable signal decoding is achieved, but silicon area and device complexity increase
Solution Approach 1:
The patent makes the single timing engine self-correcting by enabling it to monitor its own synchronization accuracy and automatically adjust its operating frequency. Instead of requiring multiple parallel engines to vote on the correct sampling rate, one engine serves itself by detecting errors and tuning its frequency to eliminate those errors, thereby achieving reliable decoding with minimal hardware.
Solution Approach 2:
The system implements feedback by having the timing engine monitor bit error rates or synchronization status and use this information to adjust its sampling frequency. This feedback loop replaces the need for multiple timing engines with a single adaptive engine that self-regulates based on received signal quality, reducing complexity while maintaining reliability.
3Device complexity
If the internal clock frequency is fixed, then device complexity is minimized, but synchronization accuracy deteriorates over temperature and lifetime
Solution Approach 1:
The patent transitions from a static fixed-frequency clock to a dynamic adjustable-frequency clock. The oscillator frequency is no longer fixed but can be dynamically tuned based on detected synchronization errors or temperature compensation requirements, allowing the system to adapt to environmental changes and maintain stability without excessive complexity.
Solution Approach 2:
The system changes the clock frequency parameter in response to measured drift or temperature variations. By allowing the oscillator frequency to vary within a controlled range based on environmental conditions and synchronization performance, the patent maintains stable synchronization over temperature and lifetime while keeping the adjustment mechanism relatively simple.
Data Source
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AI summary
A network receiver NR, 300 for a network NW, 390 using distributed clock synchronization and a method of adjusting a frequency of an internal clock of the network receiver are provided. The network receiver NR, 300 receives from the network NW, 390 a input signal 304 and has an internal clock CLK, 306 for generating a clock signal 305. The network receiver NR, 300 further comprises a clock bit comparator CBC, 312 and an adjustment signal generator ASG, 322. The clock bit comparator CBC, 312 compares lengths of a first time period lapsed while receiving at least five consecutive bits of the signal 304 and of an internal clock time interval representing the same number of bits as a number of bits of the first time period. The adjustment signal generator ASG, 322 generates a frequency adjustment signal 332 for controlling a frequency of the internal clock CLK, 306 in dependence of a result of the comparison of the lengths to reduce a difference between the lengths.