Network Relay Device Dynamic Buffer Power Control

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Solution Overview

Problem

Existing network relay devices, such as switches and routers, face challenges in reducing power consumption while maintaining performance, as their increased capacity and performance lead to higher power usage, posing issues for system maintenance and environmental impact.

Innovation Solution

Implementing a method to dynamically switch the buffer and table memory between activated and deactivated states based on traffic amounts and entry numbers, respectively, by controlling the supply of power or clock to minimize unnecessary memory usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the buffer capacity and table memory size are increased to handle larger network traffic and maintain higher performance, then the device performance and capacity are improved, but the power consumption increases

Engineering Contradiction:
Improvedevice performanceVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent applies dynamics by making the buffer and table memory configurations adjustable rather than fixed. The buffer number is dynamically changed based on received packet amounts, and table memory entries are adjusted based on required routing information, allowing the system to adapt its resource allocation to actual traffic conditions and reduce power consumption when full capacity is not needed

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes physical parameters of the system by controlling power supply and clock signals to buffer and table memory components. When traffic is low, power supply and clock signals are reduced or stopped to specific buffer regions and table memory, directly changing the operational state from full power to partial or zero power consumption while maintaining necessary functionality

Inventive Principle:
Principle #35Parameter changes

2Reliability

If all buffer regions are kept active to handle peak traffic, then the device can maintain high performance during traffic spikes, but power consumption increases during low traffic periods

Engineering Contradiction:
Improveperformance consistencyVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent segments the buffer into multiple regions that can be independently controlled. Instead of treating the buffer as a single unified resource, different buffer regions can be activated or deactivated based on traffic conditions, allowing selective power management while maintaining necessary buffering capacity for reliability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements periodic monitoring of packet reception amounts and dynamically adjusts buffer activation states accordingly. The system continuously monitors traffic patterns and periodically changes the operational state of buffer regions, switching between active and inactive states based on current traffic demands

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS8812754B2Network relay device and memory control method
Publication Date: 2014.08.19 ALAXALA NETWORKS
  • US8812754B2 patent drawing
  • US8812754B2 patent drawing
  • US8812754B2 patent drawing

AI summary

A network relay device includes a packet buffer for temporarily storing a received packet, and a packet buffer control section for changing an effective buffer number depending on the received amount of packet. When a traffic amount is small, the packet buffer control section reduces the power consumption by stopping the feeding of power or the supply of clock to a part of the packet buffers. The network relay device further includes plural table memories storing a table for deciding the transfer destination of packet, and a table memory control section for changing an effective table number according to a required number of table entries. When the required table entry number is small, the table memory control section reduces the power consumption by stopping the feeding of power or the supply of clock to a part of the table memories.