Network Relay Loop Test Method for Margin Failure Detection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing test methods for network relay apparatuses struggle to create a state where data transfer reaches performance limits within the apparatus, making it difficult to test for margin failures due to high transfer speeds and dedicated hardware configurations.

Innovation Solution

A test method that sets a transfer path in a loop shape within the network relay apparatus, inhibits TTL value decrements, and circulates a predetermined number of data packets to simulate a performance limit, allowing for the inspection of data transfer capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If test packets are transmitted using CPU at standard transmission speed, then transmission accuracy is maintained, but data transfer amount cannot reach performance limit

Engineering Contradiction:
Improvedata transfer amountVSAvoidtransmission speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The patent applies preliminary action by pre-setting the transmission speed of the packet transmitter to a value higher than the CPU's processing speed. This allows the system to accumulate a large number of test packets in the transfer path before the CPU processes them, thereby achieving the performance limit state without requiring the CPU to operate at excessive speeds during actual transmission.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements dynamics by making the transmission speed adjustable and independent from CPU speed. The packet transmitter can be configured to operate at different speeds, allowing the system to dynamically create states where the data transfer amount reaches performance limits while the CPU processes packets at its standard processing rate, thus resolving the contradiction between quantity and speed.

Inventive Principle:
Principle #15Dynamics

2Adaptability or versatility

If test processing program is added to semiconductor devices, then test functionality is provided, but packet transmission and reception performance is deteriorated

Engineering Contradiction:
Improvetest functionalityVSAvoidpacket transmission performance
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent applies segmentation by separating the test processing program from the main packet transmission and reception functions. The test program is installed in a specific semiconductor device (third semiconductor device) that is dedicated to test operations, while the first and second semiconductor devices maintain their primary packet transmission and reception functions. This segmentation allows test functionality to be added without deteriorating the performance of packet transmission and reception.

Inventive Principle:
Principle #1Segmentation

3Quantity of substance

If transfer path is set in loop shape with inhibited TTL decrement, then large number of packets can be circulated, but TTL value management becomes complex

Engineering Contradiction:
Improvenumber of circulated packetsVSAvoidTTL management complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent applies the taking out principle by extracting the TTL decrement function from the normal packet forwarding path. A specific circuit unit on the loop transfer path is configured to inhibit TTL value decrement for test packets, while other circuit units maintain normal TTL processing. This extraction allows packets to be circulated extensively in the loop without TTL exhaustion, enabling large numbers of packets to be tested without complex global TTL management mechanisms.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS7729265B2Test method for network relay apparatus and network relay apparatus
Publication Date: 2010.06.01 FUJITSU LTD
  • US7729265B2 patent drawing
  • US7729265B2 patent drawing
  • US7729265B2 patent drawing

AI summary

A transfer path in a router is set in a loop shape by a test processing unit. In a NP chip (network processor), decrement of a TTL value is inhibited by a test processing unit, and a routing table is set such that data are transmitted in order along the transfer path of the loop shape. Consequently, the test processing unit circulates a predetermined number of data on the transfer path of the loop shape, and inspects the data circulated.