Network Processor Scheduling Circuit for Load Balancing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional network processors face issues with non-optimal scheduling, leading to degraded performance and functionality due to speculative processing, single long packet flows stalling other flows, and sub-optimal use of processing resources, as well as the need for cycle-costly software locking protocols for atomic access.

Innovation Solution

A scheduling circuit that conducts work conserving, load balancing, and atomic scheduling among processing resources, eliminating the need for software locking protocols by detecting critical sequences and assigning them to a single processor for atomic execution, while cycling through flows to prevent single long flows from stalling others and ensuring efficient resource utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If speculative scheduling is used to improve resource utilization, then processor productivity increases, but system reliability deteriorates due to unpredictable performance when packets are not available

Engineering Contradiction:
Improveprocessor utilizationVSAvoidperformance predictability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The scheduling circuit automatically detects critical sequences and performs atomic scheduling without external intervention. The system self-manages the detection of critical sequences, assignment to processors, and enforcement of atomic execution, eliminating the need for external coordination mechanisms while maintaining reliable performance.

Inventive Principle:
Principle #25Self-service

2Reliability

If a single long flow is assigned to one processor to ensure atomic execution, then reliability improves, but productivity deteriorates as other flows are stalled

Engineering Contradiction:
Improveatomic execution guaranteeVSAvoidoverall system throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The scheduling circuit segments flows by detecting critical sequences and applying atomic scheduling only to those specific segments rather than entire flows. This allows non-critical portions of flows to be processed in parallel by multiple processors, maintaining atomicity where needed while maximizing overall throughput.

Inventive Principle:
Principle #1Segmentation

3Reliability

If software locking protocols are used to ensure atomic access, then reliability improves, but productivity deteriorates due to cycle-costly overhead

Engineering Contradiction:
Improveatomic access correctnessVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent replaces software-based locking protocols with a hardware scheduling circuit that performs atomic scheduling. This substitution eliminates the cycle-costly overhead of software locking by implementing critical sequence detection and atomic assignment in hardware, maintaining reliability while significantly improving processing speed.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

4Productivity

If load balancing is implemented to distribute flows evenly, then productivity improves, but reliability deteriorates when critical sequences are fragmented across processors

Engineering Contradiction:
Improveload distribution efficiencyVSAvoidatomic execution integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The scheduling circuit applies different scheduling qualities to different parts of flows based on their criticality. Critical sequences receive atomic scheduling with dedicated processor assignment, while non-critical portions benefit from load balancing. This local differentiation maintains atomic execution integrity where required while maximizing overall productivity.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11709702B2Work conserving, load balancing, and scheduling
Publication Date: 2023.07.25 INTEL CORP
  • US11709702B2 patent drawing
  • US11709702B2 patent drawing
  • US11709702B2 patent drawing

AI summary

A system and method are described for work conserving, load balancing, and scheduling by a network processor. For example, one embodiment of a system includes a plurality of processing cores, including a scheduling circuit, at least one source processing core that generates at least one task and at least one destination processing core that receives and processes the at least one task, and generates a response. The scheduling circuit of the exemplary system receives the at least one task and conducts a load balancing to select the at least one destination processing core. In an embodiment, the scheduling circuit further detects a critical sequences of tasks, schedules those tasks to be processed by a single destination processing core, and, upon completion of the critical sequence, conducts another load balancing to potentially select a different processing core to process more tasks.