Network Search Processor Rule Matching Thread Scheduling

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Solution Overview

Problem

Current packet classification methods face challenges in handling increasing network bandwidth and complexity, with existing algorithms trading memory for time and requiring significant resources, while also being inflexible and power-consuming, and existing hardware solutions like TCAMs are limited by complexity and scalability.

Innovation Solution

A method and apparatus for scheduling rule matching threads initiated by multiple processing engines in a network search processor, involving determining bundles of threads, distributing them into subgroups, assigning to scheduling queues, and prioritizing based on associated priorities, to efficiently classify packets and manage network traffic.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If traditional packet classification algorithms are used, then memory resources are increased, but processing time is reduced

Engineering Contradiction:
Improvememory resourcesVSAvoidprocessing time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent segments the packet classification task into multiple rule matching threads organized in bundles, where each thread processes a subset of rules. This segmentation allows parallel processing across multiple threads while using memory efficiently, avoiding the need to load entire rule sets into memory simultaneously, thus reducing memory usage while maintaining processing speed through concurrent execution.

Inventive Principle:
Principle #1Segmentation

2Speed

If TCAM hardware solutions are used, then packet classification speed is improved, but device complexity and scalability are worsened

Engineering Contradiction:
Improvepacket classification speedVSAvoidhardware complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent replaces complex hardware-based TCAM solutions with a software-based multi-threaded processing approach. Instead of relying on specialized hardware memory structures, the system uses general-purpose processors with optimized thread scheduling and bundle management, achieving comparable classification speeds while dramatically reducing hardware complexity and improving scalability.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Productivity

If more processing engines are added to handle increasing network bandwidth, then productivity is improved, but device complexity and power consumption are worsened

Engineering Contradiction:
Improvepacket processing capacityVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges multiple rule matching threads into bundled groups that are managed collectively by a single scheduling queue system. This consolidation allows multiple processing engines to work cooperatively on bundled thread sets, improving overall packet processing capacity while avoiding the complexity that would arise from independently managing each thread separately across multiple engines.

Inventive Principle:
Principle #5Merging (Combining)

4Loss of time

If rule matching threads are processed in parallel, then processing time is reduced, but scheduling complexity is worsened

Engineering Contradiction:
Improverule matching timeVSAvoidscheduling complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent performs preliminary organization of rule matching threads into bundled groups before parallel execution begins. Each bundle is pre-configured with its associated scheduling queue, so that when parallel processing starts, the scheduler simply needs to manage bundle-level queues rather than individual threads. This preliminary structuring dramatically reduces scheduling complexity while maintaining the benefits of parallel execution.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9130819B2Method and apparatus for scheduling rule matching in a processor
Publication Date: 2015.09.08 MARVELL ASIA PTE LTD
  • US9130819B2 patent drawing
  • US9130819B2 patent drawing
  • US9130819B2 patent drawing

AI summary

In a network search processor, configured to handle search requests in a router, a scheduler for scheduling rule matching threads initiated by a plurality of initiating engines is designed to make efficient use of the resources in the network search processor while providing high speed performance. According to at least one example embodiment, the scheduler and a corresponding scheduling method comprise: determining a set of bundles of rule matching threads, each bundle being initiated by a separate initiating engine; distributing rule matching threads in each bundle into a number of subgroups of rule matching threads; assigning the subgroups of rule matching threads associated with each bundle of the set of bundles to multiple scheduling queues; and sending rule matching threads, assigned to each scheduling queue, to rule matching engines according to an order based on priorities associated with the respective bundles of rule matching threads.