Network Switch DMA Controller for Automotive Sensor Data Transfer

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Solution Overview

Problem

Current automotive Ethernet switch devices face challenges in efficiently transferring high-bandwidth sensor data between devices within a vehicle, particularly in autonomous systems, where reliable and secure data transfer is critical for operations like braking, steering, and accelerating.

Innovation Solution

A network switch with an endpoint controller, direct memory access controller, and Ethernet switch is introduced, enabling independent data transfer between host system memory and network devices without host controller interaction, and incorporating features like IP routing and attack prevention through a TCAM controller.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data transfer is controlled through the host controller, then the host system can manage data flow, but the transfer speed and bandwidth are limited by host controller processing capability

Engineering Contradiction:
Improvedata transfer speedVSAvoidcontroller architecture complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent introduces a DMA controller as an intermediary device between the network switch and host memory. The DMA controller handles data transfer operations independently from the host controller, allowing high-speed data movement without burdening the host controller's processing capabilities. The host controller only needs to initialize the DMA controller and handle high-level data flow management, while the DMA controller manages the actual data movement at full bandwidth speeds.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the host controller manages all data transfer operations, then data security and control are maintained, but real-time attack prevention and security response are delayed

Engineering Contradiction:
Improvesecurity response reliabilityVSAvoidsecurity response time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements a TCAM controller that performs preliminary security actions by maintaining a dynamic blacklist of malicious IP addresses. The TCAM controller proactively checks incoming data packets against this blacklist before the host controller processes them, enabling real-time attack prevention. When a security threat is detected, the TCAM controller immediately blocks the malicious traffic without requiring host controller intervention, significantly reducing security response time while maintaining reliable security control.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If high-bandwidth data transfer is implemented, then sensor data can be transmitted efficiently, but the system requires more complex memory access control mechanisms

Engineering Contradiction:
Improvedata transfer bandwidthVSAvoidmemory access control complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements a buffer management system where the DMA controller autonomously manages memory buffer allocation and data transfer operations. The DMA controller independently handles buffer setup, data movement, and transfer completion without requiring continuous host controller intervention. This self-service approach enables high-bandwidth data transfer while simplifying the overall memory access control architecture, as the DMA controller's autonomous operation reduces the complexity of coordination between controllers.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11822494B2Network switch with DMA controller for independent direct memory access of host system
Publication Date: 2023.11.21 INFINEON TECHNOLOGIES AMERICAS CORP
  • US11822494B2 patent drawing
  • US11822494B2 patent drawing
  • US11822494B2 patent drawing

AI summary

A network switch includes a data bus, a register, an endpoint controller and a direct memory access controller. The endpoint controller is configured to receive a descriptor generated by a device driver of a host system, store the descriptor in the register, and transfer data between a root complex controller of the host system and the data bus. The descriptor identifies an address of a buffer in a memory of the host system. The direct memory access controller is configured to receive the address of the buffer from the endpoint controller or the register and, based on the address and an indication generated by the device driver, independently control transfer of the data between the memory of the host system and a network device connected to the network switch. The direct memory access controller is a receive direct memory access controller or a transmit direct memory access controller.