Network Switch Element Using Megaports and Crossbars
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Solution Overview
Problem
High global wire port connection counts in high-performance, high-port-count single chip switches lead to internal routing, timing, and chip area issues, necessitating a reduction in the number of connections.
Innovation Solution
The implementation of megaports with shared local routing resources and global paths on a common chip, utilizing a local crossbar for operational port communication and a global crossbar for megaport communication, along with a shared logic module for resource management and packet routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dedicated data/control paths are provided from each Ingress port to each Egress port in high port count switches, then network switching performance is improved, but global wire port connection count increases causing internal routing, timing and chip area issues
Solution Approach 1:
The patent segments the switch architecture into multiple switching elements, each handling a subset of ports. This segmentation reduces the global wire port connection count within each switching element while maintaining overall high port count functionality across the distributed switch system.
Solution Approach 2:
The patent introduces a hierarchical dimension to the switching architecture by organizing ports into groups associated with specific switching elements, and implementing inter-switch links for communication between switching elements. This dimensional organization reduces the complexity of direct port-to-port connections.
2Adaptability or versatility
If high port count is implemented on a single chip, then network connectivity is improved, but chip area increases due to high global wire port connection count
Solution Approach 1:
The switch is divided into multiple switching elements implemented on a single chip or distributed across multiple chips. Each switching element manages a subset of ports with reduced internal connections, thereby reducing the global wire port connection count and associated chip area requirements while maintaining high overall port count functionality.
Solution Approach 2:
The patent implements a nested hierarchical structure where switching elements are organized within a larger switch system. Smaller switching elements are nested within the overall switch architecture, with inter-switch links providing communication between them, allowing high port count functionality with reduced individual element complexity and area.
Data Source
AI summary
Method and system for a network switch element is provided. The switch element includes a plurality of megaports, each megaport uniquely identified by a unique megaport address identifier for network addressing. Each megaport includes a plurality of operational ports, each operational port identified by a unique operational port address identifier. The switch element also includes a local crossbar for communication between the plurality of operational ports, and a shared logic module configured to provide common control of the plurality of operational ports within a megaport to allow operational ports to share resource of a single megaport to route network packets there between. The switch element also includes a global crossbar configured to allow communication between the megaports.