Network Tap Clock Adaptation for Stable 10GBASE-T Monitoring
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Solution Overview
Problem
Existing network taps are not capable of supporting 10 Gigabit Ethernet over twisted pair cables effectively, leading to performance degradations due to conventional design limitations.
Innovation Solution
A network tap design incorporating a phase locked loop and circuitry that extracts and synchronizes clock signals between network devices, allowing for master-slave role configuration and fail-safe operation, enabling seamless 10GBASE-T Ethernet monitoring without causing network disruptions or performance degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional network tap design is used, then the network tap can monitor traffic, but it causes performance degradation and connection outages on 10GBASE-T Ethernet networks
Solution Approach 1:
The patent introduces a phase-locked loop (PLL) as an intermediary component that receives clock signals from one network port and provides synchronized clock signals to another network port. This mediator ensures that clock signals are properly synchronized across the tap device, preventing the performance degradation and bit error rate issues that occur in conventional designs where clock signals are not properly managed.
Solution Approach 2:
The patent changes the clock signal parameters by extracting, synchronizing, and retransmitting clock signals through the PLL. By adjusting and synchronizing the clock signal parameters (frequency, phase) between network ports, the system maintains reliable 10GBASE-T Ethernet operation while enabling traffic monitoring, thus resolving the contradiction between monitoring capability and network performance.
2Device complexity
If clock signals are not synchronized between network ports, then the network tap structure is simpler, but performance degradation occurs
Solution Approach 1:
The phase-locked loop serves as a dedicated intermediary component that handles the complex task of clock signal synchronization. By offloading this function to a specialized PLL circuit, the overall system achieves reliable synchronized operation without requiring complex distributed synchronization logic across multiple components.
Solution Approach 2:
The PLL circuit automatically performs clock signal extraction, synchronization, and adjustment without requiring external intervention or complex control logic. The self-service nature of the PLL in locking onto and synchronizing clock signals simplifies the overall system design while ensuring reliable operation.
3Adaptability or versatility
If a network tap is inserted into 10GBASE-T Ethernet, then traffic monitoring is enabled, but connection outages and performance degradation occur
Solution Approach 1:
The PLL acts as a mediator between the network ports, ensuring that clock signals are properly synchronized as traffic passes through the tap. This intermediary function allows the tap to monitor traffic without disrupting the timing-critical 10GBASE-T Ethernet communication, thereby maintaining connection stability while enabling monitoring capability.
Solution Approach 2:
The system changes the clock signal parameters through the PLL to match the requirements of 10GBASE-T Ethernet operation. By properly adjusting and synchronizing clock frequency and phase parameters, the tap enables traffic monitoring while maintaining the precise timing requirements necessary for reliable high-speed Ethernet connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures synchronized clock signals across network ports, preventing performance degradations and allowing for reliable 10GBASE-T Ethernet monitoring with minimal impact on network devices, maintaining connectivity and reducing the risk of outages or bit error rate degradation.
Implementation Method 1
a phase locked loop, and circuitry connecting an output of said first network connector to an input of said second network connector
Data Source
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AI summary
The invention relates to a network tap (150) comprising a first network connector (11), a second network connector (12), a third network connector (13) for connecting to a monitoring device (123), a phase locked loop (51), and circuitry (20,40,60). The circuitry is configured to extract a clock signal from a first signal on an output of one of the first and second network connectors, provide the clock signal to the phase locked loop, receive a reference clock signal derived from the recovered clock signal from the phase locked loop and clock a second signal on the input of the other one of the first and second network connectors using the received reference clock signal if a link has been established between a first network device (121) and the first network connector and a link has been established between a second network device (122) and the second network connector.