Network Tap Clock Adaptation for Stable Ethernet Links
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Solution Overview
Problem
Conventional network taps can cause performance degradations and connection issues due to improper clock synchronization in Gigabit and 10 Gigabit Ethernet systems, especially in environments requiring Auto-Negotiation and Synchronous Ethernet support.
Innovation Solution
A network tap design that includes a phase locked loop and circuitry to extract and synchronize clock signals between network devices, forcing master-slave roles and using a free running clock to establish links, even without synchronization signals, thereby ensuring synchronized clocks and avoiding performance degradations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional network tap is used in Gigabit Ethernet systems, then network traffic monitoring is enabled, but performance degradation and connection issues occur due to improper clock synchronization
Solution Approach 1:
The patent introduces a phase-locked loop (PLL) as an intermediary component that mediates between the two Ethernet interfaces. The PLL extracts clock signals from incoming data, generates synchronized reference clocks, and distributes them to clock the outgoing data paths. This intermediary clock synchronization mechanism resolves the timing conflicts that would otherwise cause performance degradation and connection instability in conventional network taps.
Solution Approach 2:
The patent dynamically adjusts clock signal parameters (frequency, phase) through the PLL to match the requirements of different Ethernet interfaces. By changing the clock signal parameters based on the detected data rate and interface requirements, the system achieves proper synchronization without causing performance degradation, resolving the contradiction between reliability and the complexity of manual clock configuration.
2Adaptability or versatility
If Auto-Negotiation is implemented in the network tap, then master-slave timing control is established, but performance degradations occur due to improper clocking of transmitted signals
Solution Approach 1:
The patent implements a feedback mechanism where the PLL continuously monitors the clock signals extracted from incoming data and adjusts the reference clock generation accordingly. This feedback loop ensures that the clocked transmission maintains proper synchronization with the negotiated rate, preventing performance degradations while fully supporting Auto-Negotiation for master-slave timing control.
Solution Approach 2:
The patent performs preliminary clock synchronization by extracting and processing clock signals from incoming data before the actual data transmission occurs. The PLL generates reference clocks in advance, ensuring that when Auto-Negotiation establishes master-slave timing control, the clocking of transmitted signals is already properly configured, thereby avoiding performance degradations.
3Reliability
If the network tap uses recovered clock signals to clock transmitted data, then clock synchronization is achieved, but connection outages may occur during link establishment
Solution Approach 1:
The patent performs preliminary clock signal extraction and PLL synchronization during the link establishment phase, before full data transmission begins. By having the PLL ready with synchronized reference clocks before the link is fully established, the system avoids connection outages that would occur if clock synchronization had to be established after the link was already up.
Solution Approach 2:
The patent prepares the clock synchronization mechanism in advance by having the PLL continuously ready to provide reference clocks. This beforehand cushioning ensures that when link establishment occurs, the clocking is already synchronized and stable, preventing connection outages and reducing the duration of the link establishment process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures synchronized network connections, preventing performance degradations and maintaining network integrity by synchronizing clocks and managing master-slave roles effectively, even in systems without explicit synchronization signals, thus supporting 10 Gigabit Ethernet over twisted pair cables without causing connection outages or bit error rate degradation.
Implementation Method 1
a phase locked loop, and circuitry connecting an output of said first network connector to an input of said second network connector
Data Source
AI summary
A network tap includes a first network connector, a second network connector, a third network connector for connecting to a monitoring device, a phase locked loop, and circuitry. The circuitry is configured to extract a clock signal from a first signal on an output of one of the first and second network connectors, provide the clock signal to the phase locked loop, receive a reference clock signal derived from the recovered clock signal from the phase locked loop and clock a second signal on the input of the other one of the first and second network connectors using the received reference clock signal if a link has been established between a first network device and the first network connector and a link has been established between a second network device and the second network connector.