Network Time Synchronization Using Physical-Layer Clock Recovery

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Solution Overview

Problem

Existing time synchronization methods, such as NTP, PTP, WhiteRabbit, and GNSS, face challenges in achieving precise and reliable time synchronization due to limitations in protocol complexity, hardware requirements, and environmental vulnerabilities.

Innovation Solution

A time synchronization device and network that utilize a time-estimating device to synchronize with non-time-estimating devices, employing a communication section, clock section, frequency comparison sections, and estimation processing to achieve high-precision time synchronization without dedicated ICs and satellite radio waves.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If NTP or PTP protocols are used for time synchronization, then a large number of nodes can be synchronized with simple configuration, but precise time synchronization cannot be achieved

Engineering Contradiction:
Improveconfiguration simplicityVSAvoidtime synchronization precision
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The patent replaces application-layer protocol-based time synchronization (NTP/PTP) with a physical-layer frequency comparison mechanism. By comparing clock frequencies directly at the physical layer and using phase-locked loops to synchronize clock signals, the system achieves nanosecond-level precision while maintaining configuration simplicity. The frequency comparison section and phase synchronization section enable direct physical-layer synchronization without complex protocol stacks.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Measurement precision

If WhiteRabbit is used for precise time synchronization, then high accuracy of several nanoseconds is achieved, but a dedicated IC is required in each node making the system complicated

Engineering Contradiction:
Improvetime synchronization accuracyVSAvoidhardware configuration complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent creates a universal time synchronization mechanism that can be implemented using standard communication interfaces and clock circuits already present in most digital systems. The frequency comparison section can utilize existing PLL circuits and clock generators, eliminating the need for dedicated WhiteRabbit ICs. The system achieves similar nanosecond-level accuracy using components that are part of standard digital system architecture.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Measurement precision

If GNSS is used for time synchronization, then precise time information is provided by satellite radio waves, but the system is vulnerable to antenna failure, solar wind deterioration, and jamming

Engineering Contradiction:
Improvetime information accuracyVSAvoidsynchronization reliability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent introduces a local frequency comparison and phase synchronization mechanism as an intermediary between external time sources and node clocks. The frequency comparison section locally compares frequencies and the phase synchronization section maintains phase coherence, creating a resilient synchronization system that does not depend on vulnerable satellite radio wave reception. This intermediary mechanism provides continuous synchronization even when GNSS signals are unavailable or jammed.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12289390B2Time synchronization device and network
Publication Date: 2025.04.29 NAT INST OF INFORMATION & COMM TECH
  • US12289390B2 patent drawing
  • US12289390B2 patent drawing
  • US12289390B2 patent drawing

AI summary

A node includes: a communication module that recovers a clock signal of another node; a high-precision clock module; a first phase/frequency comparison module; a time estimation section that estimates time information of each node; a counter value correction section that corrects a counter value; a fractional PLL; a second phase/frequency comparison module; and a division ratio correction section that corrects a division ratio of the fractional PLL.