Network Time Transfer with Unified Clock Delay Compensation

The patent implements feedback mechanisms through phase detectors that continuously monitor phase differences between reference and synthesized clocks, and through delay lock loops that adjust synthesis parameters based on measured delays. This feedback control eliminates uncontrolled phase transients by continuously correcting quantization errors and phase noise, thereby improving time transfer accuracy while suppressing harmful phase variations.

The patent changes the parameter representation from fixed quantized values to continuously adjustable parameters. By using delay lock loops that can precisely control synthesis clock delays and phase detectors that provide continuous phase difference measurements, the system transforms discrete quantized phase adjustments into continuous parameter control, eliminating phase transients caused by quantization errors.

The patent introduces intermediary components - phase detectors and delay lock loops - that mediate between the reference clock and synthesized clocks. These intermediaries simplify the synchronization architecture by providing standardized interfaces for phase measurement and delay control, reducing overall system complexity while maintaining high time transfer precision through their specialized functions.

The patent segments the time transfer function into distinct modular components: phase detectors for measurement, delay lock loops for control, and synthesized clocks for time generation. This segmentation allows each component to be optimized independently and simplifies the overall system architecture, reducing complexity while achieving precise time transfer through coordinated operation of the segmented modules.

The patent extracts and separates the residence time component from the frequency alignment calculation. By using delay lock loops to specifically measure and compensate for propagation delays, and phase detectors to measure phase differences, the system extracts timing information about residence times while using separate mechanisms for frequency alignment, preventing residence time variations from degrading alignment accuracy.

The patent segments the timing information into distinct components: propagation delay measured by delay lock loops, phase difference measured by phase detectors, and frequency offset measured by frequency detectors. This segmentation allows complete timing information to be captured while frequency alignment accuracy is maintained by using dedicated measurement mechanisms for each parameter, preventing cross-contamination of measurement errors.