Network Device Time Synchronization via PLL and TOD Distribution
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Solution Overview
Problem
Network devices face challenges in maintaining accurate time synchronization across components, which is crucial for latency measurements and time-stamping operations, due to variations in clock signals and time of day representations.
Innovation Solution
A method and system that distribute a synchronized clock signal and time of day information from redundant system control devices to network chips through a phase-locked loop chip, ensuring all components operate on a unified time base, with mechanisms to handle failures and adjust for deterministic delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple independent clock sources are used in different system control devices, then system reliability is improved through redundancy, but time synchronization precision deteriorates due to clock variations
Solution Approach 1:
A TOD message is introduced as an intermediary carrier that transports time reference information from the active SCD to the standby SCD. The standby SCD uses this TOD message to synchronize its internal clock, thereby maintaining time precision across redundant systems. The TOD message acts as the mediator that resolves the contradiction by enabling precise time transfer without requiring direct clock coupling.
Solution Approach 2:
The system implements feedback through the continuous exchange of TOD messages between active and standby SCDs. The standby SCD receives TOD messages from the active SCD and adjusts its clock accordingly, creating a closed-loop synchronization mechanism. This feedback ensures that even with independent clock sources, time precision is maintained through continuous correction based on the active SCD's time reference.
2Adaptability or versatility
If clock signals are distributed across multiple components, then system coverage and functionality are improved, but time base consistency deteriorates due to transmission delays and variations
Solution Approach 1:
The system performs preliminary synchronization by having the standby SCD continuously receive and process TOD messages from the active SCD before any failover occurs. This preliminary action ensures that when switching happens, the standby SCD is already synchronized to the active SCD's time base, eliminating synchronization disruptions and maintaining time base consistency across the distributed system.
Solution Approach 2:
The TOD message serves as an intermediary that carries precise time reference information from the active SCD to the standby SCD and network chips. This intermediary mechanism allows wide system coverage through distributed clock distribution while maintaining time base consistency by having all components reference the same active SCD's time through the TOD message carrier.
3Reliability
If redundant system control devices are implemented, then system availability is improved, but system complexity increases due to synchronization management
Solution Approach 1:
The standby SCD autonomously manages its own synchronization by automatically receiving TOD messages from the active SCD and adjusting its internal clock without external intervention. This self-service mechanism simplifies the overall system complexity because each SCD independently handles its synchronization state, eliminating the need for complex centralized synchronization control logic.
Solution Approach 2:
The feedback mechanism through TOD message exchange automates the synchronization management process. The standby SCD continuously monitors incoming TOD messages and automatically adjusts its clock, creating a self-regulating system. This feedback-driven approach reduces synchronization management complexity by replacing manual or centralized control with automated distributed feedback loops.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides a robust, precise, and universal time base for network devices, enabling accurate time-stamping and latency measurements by synchronizing all network chips to a single time base, even in the event of system failures, and compensating for transmission delays.
Implementation Method 1
synchronizing a third clock signal, generated by the PLL chip, to the first clock signal
Data Source
AI summary
A method for distributing time information in network devices. The method includes sending a first clock signal from a first system control device (SCD) to a PLL chip, sending a first time of day (TOD) from the first SCD to a line card system control device (LC-SCD), sending a second clock signal from a second SCD to the PLL chip and sending a second TOD from the second SCD to the LC-SCD. The method further includes synchronizing a third clock signal, generated by the PLL chip, to the first clock signal, if the first SCD is operational. The method further includes sending the third clock signal to a network chip, deriving, using the third clock signal, a first network-chip-internal clock signal and applying the first network-chip-internal clock signal to increment a network-chip-internal TOD to obtain a third TOD. The method further includes synchronizing the third TOD to the first TOD.