Network Timing Reference Compensation for Wander Reduction
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Solution Overview
Problem
In wide area networks, cascaded timing reference distribution schemes introduce noise and errors due to internal and external Gaussian noise, leading to timing reference wander and degradation, which can exceed accuracy thresholds and increase system costs.
Innovation Solution
A network component with a comparison and voting logic function, compensation logic, and delay function is used to compare internal timing references, calculate offset values, and add them to timing references to compensate for noise, thereby reducing wander and improving synchronization accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If cascaded timing reference distribution is used to extend network coverage, then the number of nodes that can forward timing references increases, but timing reference accuracy degrades due to accumulated noise and wander
Solution Approach 1:
The patent implements feedback by continuously monitoring the timing reference signal quality at each node and using Phase-Locked Loops (PLLs) to detect deviations. The system feeds back correction signals to compensate for accumulated noise and wander, allowing extended network coverage while maintaining timing accuracy through active error correction mechanisms.
Solution Approach 2:
The patent changes key parameters including implementing jitter attenuation filters with specific time constants, adjusting PLL bandwidths, and applying temperature compensation to timing components. These parameter changes reduce the impact of noise accumulation over distance, enabling extended coverage while preserving timing reference accuracy.
2Loss of energy
If more nodes forward timing references without retransmission, then system costs reduce, but noise-induced wander increases and exceeds accuracy thresholds
Solution Approach 1:
The patent applies preliminary action by pre-compensating for expected noise accumulation and wander before the timing reference degrades beyond acceptable thresholds. Each node proactively adjusts timing parameters and applies corrections in advance, preventing reliability degradation while allowing extended forwarding chains without retransmission.
Solution Approach 2:
The patent implements beforehand cushioning by designing the timing distribution architecture with built-in margin and redundancy. Jitter attenuation filters and temperature-compensated oscillators provide a cushion against noise accumulation, allowing the system to tolerate longer forwarding chains without exceeding accuracy thresholds or requiring costly retransmission.
3Device complexity
If standard timing reference distribution is used, then device complexity remains low, but timing reference wander exceeds acceptable limits due to Gaussian noise
Solution Approach 1:
The patent applies local quality by implementing targeted improvements at specific critical points in the distribution chain rather than throughout the entire system. Jitter attenuation filters are placed at strategic locations, and temperature compensation is applied to key timing components. This selective approach reduces wander while minimizing added complexity compared to comprehensive system-wide modifications.
Data Source
AI summary
A network component comprising a first adaptation component, a second adaptation component, a system Phase-Locked-Loop (PLL) coupled to the first adaptation component, a comparison and voting logic component coupled to the first adaptation component and the system PLL component, a compensation logic component coupled to the comparison and voting logic component, and a positive/negative delay component coupled to the second adaptation component and the compensation logic component. Also disclosed is a network component comprising a comparison and voting logic function block configured to compare a plurality of internal timing references in a system PLL synchronization area, a compensation logic function block configured to calculate an offset value if any of the internal references substantially deviates from an expected value in a deterministic outcome, and a delay function block configured to add the calculated offset value to a timing reference that is forwarded to a subsequent node.