Network Verification Using Hierarchy-Based Binary Decision Diagrams
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Solution Overview
Problem
Existing network verification techniques face challenges such as scalability issues, slow execution, and the inability to precisely locate the source of faults due to state explosion and excessive computing power, particularly in large and complex networks.
Innovation Solution
The use of hierarchy-based models and binary decision diagrams (BDDs) to aggregate network entities, allowing for granular verification by processing each device and network entity level sequentially, enabling precise fault localization and reducing state explosion through logical combinations and index variables.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional network testing tools (SNMP, tracert, ping) are used to verify network configurations, then the tools can reactively diagnose problematic issues after they occur, but they provide limited coverage of the network and cannot proactively identify issues
Solution Approach 1:
The patent creates a virtual copy of the network topology and configurations using BDD data structures, allowing verification to be performed on the copied model rather than the actual network. This enables comprehensive proactive verification without disrupting real network operations, resolving the contradiction between verification reliability and verification coverage.
2Reliability
If formal verification techniques are applied to network verification, then proactive and predictive identification of issues is achieved, but scalability and real-time verification remain challenging
Solution Approach 1:
The patent segments the network verification process into modular components: topology representation using BDDs, configuration modeling, and verification engine. Each component operates independently and can process network segments separately, enabling scalable verification of large networks while maintaining proactive issue identification capabilities.
Solution Approach 2:
The patent changes the parameter representation from traditional state-space models to BDD-based parameter encodings. This transformation allows the verification system to handle larger network states efficiently by exploiting the compact representation and manipulation capabilities of BDDs, thus improving scalability.
3Reliability
If existing network verification techniques (model checking, theorem proving, SAT/SMT solver) are used, then network properties can be verified, but the techniques are slow to execute or require excessive computing power
Solution Approach 1:
The patent substitutes traditional mechanical verification approaches (model checking, theorem proving) with a BDD-based symbolic execution engine. This substitution leverages the efficient manipulation properties of BDDs to perform verification operations much faster, reducing execution time while maintaining verification reliability.
4Measurement precision
If detailed network modeling is performed to locate fault sources precisely, then fault localization accuracy is improved, but state explosion occurs and computing resources are excessive
Solution Approach 1:
The patent introduces a new dimensional approach by representing network states in the BDD dimension rather than traditional state-space dimension. This dimensional transformation allows precise fault localization through BDD variable and term analysis without suffering from state explosion, as BDDs compactly represent and manipulate large state spaces.
Data Source
AI summary
Methods and systems for network verification are described. An input binary decision diagram (BDD) is defined to represent an input header space to query for a network property of interest. The input BDD is provided as input to a device-level BDD representing a source device in a logical topology representing connections among devices of the network. Each device in the network is represented by a respective device-level BDD in the logical topology. An output BDD is calculated, representing an output header space outputted by a destination device in the logical topology. The output BDD is calculated by sequentially applying, to the input BDD, each device-level BDD in a logical path from the source device to the destination device. The output BDD is then reported, and the reported output BDD is compared with an expected output BDD, to verify the network property of interest.