Network Verification Using Compact Forwarding Behavior Representation
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Solution Overview
Problem
Conventional network verification methods are inefficient and semi-automated, requiring expertise and failing to detect subtle data plane bugs, while they verify data and control planes in isolation and only check single data planes at a time, leading to inefficiencies and false alarms.
Innovation Solution
The implementation of a real-time 'delta-net' network verification method that constructs a single compact representation of forwarding behavior, using lattice-theoretical abstract domains and edge-labelled graphs to represent all packet flows, allowing for incremental updates and efficient detection of errors in the data plane.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional network verification methods are used, then network verification can be performed, but the verification process is inefficient and produces false alarms
Solution Approach 1:
The patent segments the network verification process into separate data plane and control plane verifications, and further divides the data plane verification into individual switch verifications. Each switch's forwarding table is verified independently by checking reachability from each destination prefix to all other prefixes, allowing for targeted and efficient verification without false alarms from correlated errors.
Solution Approach 2:
The patent implements feedback mechanisms where the verification process uses the results of individual prefix reachability checks to determine overall data plane correctness. The system feeds back verification results to identify specific problematic prefixes and switches, enabling precise error localization and eliminating false alarms through systematic validation.
2Device complexity
If data plane and control plane are verified in isolation, then verification complexity is reduced, but subtle data plane bugs are not detected
Solution Approach 1:
The patent performs preliminary verification of the data plane forwarding tables before control plane verification. By first establishing correct data plane behavior through prefix-based reachability checks, the system creates a validated foundation that enables more effective control plane verification and reveals subtle bugs that would otherwise remain undetected.
3Productivity
If multiple data planes are verified simultaneously, then verification throughput is increased, but computational overhead increases
Solution Approach 1:
The patent segments verification into hierarchical levels: individual prefix reachability checks within each switch, individual switch verifications, and aggregate data plane verification. This segmentation allows parallel processing of independent switches while maintaining computational efficiency through the structured organization of verification tasks.
Solution Approach 2:
The patent performs verification for each destination prefix to all other prefixes in the data plane, which may seem excessive but enables comprehensive coverage. This partial verification approach at the prefix level aggregates to complete data plane verification, allowing parallel execution without redundant computations.
Data Source
AI summary
A network verification method may include identifying a data plane including one or more forwarding tables for each switch of a plurality of switches in the data plane. The method may also include generating a forwarding behavior representation of the data plane to represent Boolean combinations of forwarding rules of the one or more forwarding tables of the data plane. Further, the method may include comparing the forwarding behavior representation of the data plane to one or more network properties to detect one or more errors in the data plane.