Generalized Network VLSI Layouts With Shuffle Links for Lower Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing VLSI layouts of multi-stage interconnection networks like Benes and butterfly fat tree networks are inefficient and complex, leading to large area requirements, increased power consumption, and longer signal latency on semiconductor chips.
Innovation Solution
The development of VLSI layouts for generalized multi-stage networks that utilize only horizontal and vertical links, employing shuffle exchange links to connect switches across sub-integrated circuit blocks, thereby reducing cross points and signal latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional VLSI layouts of multi-stage interconnection networks are used, then full connectivity is achieved, but the area requirement increases significantly
Solution Approach 1:
The patent transforms the traditional two-dimensional grid-based interconnection network into a three-dimensional stacked architecture. Multiple layers are interconnected through vertical vias, enabling full connectivity while reducing the footprint area. The 3D arrangement allows more efficient routing paths and reduces the need for extensive horizontal wiring, thus achieving the same connectivity with smaller area.
Solution Approach 2:
The patent implements a hierarchical structure where switching elements are organized in nested stages across multiple layers. Each layer contains switching elements that are interconnected with elements on adjacent layers, creating a compact nested arrangement. This nesting allows the network to maintain full connectivity while efficiently utilizing the available space, as smaller switching elements are embedded within larger structural frameworks.
2Adaptability or versatility
If traditional VLSI layouts with extensive wiring are used, then connectivity is maintained, but power consumption increases
Solution Approach 1:
By moving to a 3D stacked architecture, the patent reduces the average wire length required to connect any two points in the network. Vertical vias provide direct short-distance connections between layers, eliminating the need for long horizontal wires that would traverse the entire chip. This dimensional transition significantly reduces capacitive loading and dynamic power consumption associated with charging and discharging long wire segments.
Solution Approach 2:
The patent implements localized switching elements and routing resources within each layer, rather than relying on global wiring across the entire chip. Each switching element has dedicated local connections to adjacent layers and elements, reducing the need for long-distance signal transmission. This localization of connectivity reduces the overall wire length and associated power consumption while maintaining full network connectivity.
3Ease of manufacture
If traditional grid-based routing is used, then layout simplicity is maintained, but signal latency increases
Solution Approach 1:
The 3D stacked architecture introduces vertical routing dimensions that provide direct pathways between layers. Signals can travel vertically through short via connections rather than traversing long horizontal paths across multiple grid cells. This dimensional addition creates more direct routing options, reducing the number of routing hops and the physical distance signals must travel, thereby decreasing latency while maintaining manufacturing simplicity through standard CMOS processes.
Solution Approach 2:
The patent divides the interconnection network into multiple independent layers, each handling specific routing functions. This segmentation allows signals to be routed through optimized paths in different layers, avoiding congestion and delays that would occur in a monolithic 2D grid. Each layer can be independently designed and optimized, maintaining ease of manufacture while achieving lower overall signal latency through parallel routing capabilities.
Data Source
AI summary
In accordance with the invention, VLSI layouts of generalized multi-stage networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links. The VLSI layouts employ shuffle exchange links where outlet links of cross links from switches in a stage in one sub-integrated circuit block are connected to inlet links of switches in the succeeding stage in another sub-integrated circuit block so that said cross links are either vertical links or horizontal and vice versa. In one embodiment the sub-integrated circuit blocks are arranged in a hypercube arrangement in a two-dimensional plane. The VLSI layouts exploit the benefits of significantly lower cross points, lower signal latency, lower power and full connectivity with significantly fast compilation.The VLSI layouts presented are applicable to generalized multi-stage networks V(N1, N2, d, s), generalized folded multi-stage networks Vfold(N1, N2, d, s), generalized butterfly fat tree networks Vbft(N1, N2, d, s), generalized multi-link multi-stage networks Vmlink(N1, N2, d, s), generalized folded multi-link multi-stage networks Vfold-mlink(N1, N2, d, s), generalized multi-link butterfly fat tree networks Vmlink-bft(N1, N2, d, s), and generalized hypercube networks Vhcube(N1, N2, d, s) for s=1, 2, 3 or any number in general. The embodiments of VLSI layouts are useful in wide target applications such as FPGAs, CPLDs, pSoCs, ASIC placement and route tools, networking applications, parallel & distributed computing, and reconfigurable computing.